Conformal copper deposition on thin liner layer
US-2025333845-A1 · Oct 30, 2025 · US
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Kolics Artur patents
Kolics Artur is listed as an inventor on 61 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Kolics Artur |
| Total patents | 61 |
| First publication | Feb 5, 2015 |
| Latest publication | Oct 30, 2025 |
Notable patents
Publications ranked by popularity score, then publication date.
Vacuum-integrated hardmask processes and apparatus
US-2025053080-A1 · Feb 13, 2025 · US
Vacuum-integrated hardmask processes and apparatus
US-2023273516-A1 · Aug 31, 2023 · US
Vacuum-integrated hardmask processes and apparatus
US-2023266662-A1 · Aug 24, 2023 · US
Vacuum-integrated hardmask processes and apparatus
US-2022075260-A1 · Mar 10, 2022 · US
Vacuum-integrated hardmask processes and apparatus
US-11209729-B2 · Dec 28, 2021 · US
Vacuum-integrated hardmask processes and apparatus
US-10831096-B2 · Nov 10, 2020 · US
Vacuum-integrated hardmask processes and apparatus
US-2020089104-A1 · Mar 19, 2020 · US
Vacuum-integrated hardmask processes and apparatus
US-10514598-B2 · Dec 24, 2019 · US
Via prefill in a fully aligned via
US-2019363048-A1 · Nov 28, 2019 · US
Recent patents
Latest publications not already listed above.
Interlevel conductor pre-fill utilizing selective barrier deposition
US-10262943-B2 · Apr 16, 2019 · US
Vacuum-integrated hardmask processes and apparatus
US-2019094685-A1 · Mar 28, 2019 · US
Methods for wet metal seed deposition for bottom up gapfill of features
US-10103056-B2 · Oct 16, 2018 · US
Metallization of the wafer edge for optimized electroplating performance on resistive substrates
US-10079207-B2 · Sep 18, 2018 · US
Method for selectively sealing ultra low-k porous dielectric layer using flowable dielectric film formed from vapor phase dielectric precursor
US-10049921-B2 · Aug 14, 2018 · US
Interlevel Conductor Pre-Fill Utilizing Selective Barrier Deposition
US-2018151503-A1 · May 31, 2018 · US
Interlevel conductor pre-fill utilizing selective barrier deposition
US-9875968-B2 · Jan 23, 2018 · US
Vacuum-integrated hardmask processes and apparatus
US-2018004083-A1 · Jan 4, 2018 · US
Atomic layer etching for enhanced bottom-up feature fill
US-9837312-B1 · Dec 5, 2017 · US
Metallization of the wafer edge for optimized electroplating performance on resistive substrates
US-2017330831-A1 · Nov 16, 2017 · US
Method of electroless plating using a solution with at least two borane containing reducing agents
US-9818617-B2 · Nov 14, 2017 · US
Vacuum-integrated hardmask processes and apparatus
US-9778561-B2 · Oct 3, 2017 · US
Dual damascene fill
US-9768063-B1 · Sep 19, 2017 · US
Metallization of the wafer edge for optimized electroplating performance on resistive substrates
US-9761524-B2 · Sep 12, 2017 · US
Pre-fill wafer cleaning formulation
US-2017207091-A9 · Jul 20, 2017 · US
Pre-fill wafer cleaning formulation
US-9691622-B2 · Jun 27, 2017 · US
Interlevel Conductor Pre-Fill Utilizing Selective Barrier Deposition
US-2017162512-A1 · Jun 8, 2017 · US
Electroless plating solution with at least two borane containing reducing agents
US-2017092499-A1 · Mar 30, 2017 · US
Interlevel conductor pre-fill utilizing selective barrier deposition
US-9583386-B2 · Feb 28, 2017 · US
Electroless plating solution with at least two borane containing reducing agents
US-9551074-B2 · Jan 24, 2017 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Lam Res Corp | 61 |
| Kolics Artur | 4 |
| Li Nanhai | 2 |
| Rulkens Ron | 1 |
| Jain Aman | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10P14/46 | 33 |
| H10W20/056 | 27 |
| H10W20/057 | 23 |
| H10W20/425 | 21 |
| H01L21/288 | 19 |