Metallization of the wafer edge for optimized electroplating performance on resistive substrates

US2017330831A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2017330831-A1
Application numberUS-201715665017-A
CountryUS
Kind codeA1
Filing dateJul 31, 2017
Priority dateJun 2, 2014
Publication dateNov 16, 2017
Grant date

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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Abstract

Official abstract text for this publication.

A substrate having at least one device; wherein the substrate having a conductive layer disposed on a top surface of the substrate, the top surface having an edge exclusion region defined as an annular area that extends to an edge of the substrate, the top surface of the substrate further having a process region defined as a central area of the substrate that extends to about the annular area; wherein the substrate having a metallic material deposited over the conductive layer at the edge exclusion region, wherein a thickness of the metallic material reduces electrical resistance of the metallic material at the edge exclusion region; wherein the thickness of the metallic material and resulting reduced electrical resistance for an applied electrical current to the metallic material facilitates increasing a rate at which the process region is plated as a result of the applied electrical current and an applied electroplating solution.

First claim

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What is claimed is: 1 . A substrate, comprising: the substrate having at least one device; wherein the substrate having a conductive layer disposed on a top surface of the substrate, the top surface of the substrate having an edge exclusion region defined as an annular area that extends to an edge of the substrate, the top surface of the substrate further having a process region defined as a central area of the substrate that extends to about the annular area; wherein the substrate having a metallic material deposited over the conductive layer at the edge exclusion region, wherein a thickness of the metallic material reduces electrical resistance of the metallic material at the edge exclusion region; wherein the thickness of the metallic material and resulting reduced electrical resistance for an applied electrical current to the metallic material facilitates increasing a rate at which the process region is plated as a result of the applied electrical current and an applied electroplating solution. 2 . The substrate of claim 1 , wherein the conductive layer defines a metallic seed layer; and wherein the applied electrical current to the metallic material effects plating of a metallic bulk layer over the process region of the substrate. 3 . The substrate of claim 1 , wherein the conductive layer defines a liner layer or a barrier layer; and wherein the applied electrical current to the metallic material effects plating of a metallic seed layer or a metallic bulk layer over the process region of the substrate. 4 . The substrate of claim 1 , wherein the metallic material is configured to accommodate electrical contacts that contact the metallic material, the electrical contacts being distributed around the annular area of the edge exclusion region when contacting the metallic material; wherein the electrical current is applied to the metallic material via the electrical contacts while the electroplating solution is applied over the process region of the substrate. 5 . The substrate of claim 4 , wherein the metallic material is further configured to accommodate an annular seal configured to contact the metallic material and prevent the electroplating solution from contacting the electrical contacts. 6 . The substrate of claim 1 , wherein increasing the rate at which the process region is plated is defined by increasing the applied electrical current while the electroplating solution is applied over the process region of the substrate, the thickness of the metallic material and resulting reduced electrical resistance facilitating increasing the applied electrical current. 7 . The substrate of claim 1 , wherein the rate at which the process region is plated increases from an initial rate to an increased rate that is approximately linearly correlated to the thickness of the metallic material. 8 . A substrate, comprising: the substrate having at least one device; wherein the substrate having a conductive layer disposed on a top surface of the substrate, wherein the conductive layer defines a metallic seed layer, the top surface of the substrate having an edge exclusion region defined as an annular area that extends to an edge of the substrate, the top surface of the substrate further having a process region defined as a central area of the substrate that extends to about the annular area; wherein the substrate having a metallic material deposited over the conductive layer at the edge exclusion region, wherein a thickness of the metallic material reduces electrical resistance of the metallic material at the edge exclusion region; wherein the thickness of the metallic material and resulting reduced electrical resistance for an applied electrical current to the metallic material facilitates increasing a rate at which the process region is plated as a result of the applied electrical current and an applied electroplating solution, wherein the applied electrical current to the metallic material effects plating of a metallic bulk layer over the process region of the substrate; wherein the metallic material is configured to accommodate electrical contacts that contact the metallic material, the electrical contacts being distributed around the annular area of the edge exclusion region when contacting the metallic material; wherein the electrical current is applied to the metallic material via the electrical contacts while the electroplating solution is applied over the process region of the substrate. 9 . The substrate of claim 8 , wherein the metallic material is further configured to accommodate an annular seal configured to contact the metallic material and prevent the electroplating solution from contacting the electrical contacts. 10 . The substrate of claim 8 , wherein increasing the rate at which the process region is plated is defined by increasing the applied electrical current while the electroplating solution is applied over the process region of the substrate, the thickness of the metallic material and resulting reduced electrical resistance facilitating increasing the applied electrical current. 11 . The substrate of claim 8 , wherein the rate at which the process region is plated increases from an initial rate to an increased rate that is approximately linearly correlated to the thickness of the metallic material. 12 . A substrate, comprising: the substrate having at least one device; wherein the substrate having a conductive layer disposed on a top surface of the substrate, wherein the conductive layer defines a liner layer or a barrier layer, the top surface of the substrate having an edge exclusion region defined as an annular area that extends to an edge of the substrate, the top surface of the substrate further having a process region defined as a central area of the substrate that extends to about the annular area; wherein the substrate having a metallic material deposited over the conductive layer at the edge exclusion region, wherein a thickness of the metallic material reduces electrical resistance of the metallic material at the edge exclusion region; wherein the thickness of the metallic material and resulting reduced electrical resistance for an applied electrical current to the metallic material facilitates increasing a rate at which the process region is plated as a result of the applied electrical current and an applied electroplating solution, wherein the applied electrical current to the metallic material effects plating of a metallic seed layer or a metallic bulk layer over the process region of the substrate; wherein the metallic material is configured to accommodate electrical contacts that contact the metallic material, the electrical contacts being distributed around the annular area of the edge exclusion region when contacting the metallic material; wherein the electrical current is applied to the metallic material via the electrical contacts while the electroplating solution is applied over the process region of the substrate. 13 . The substrate of claim 12 , wherein the metallic material is further configured to accommodate an annular seal configured to contact the metallic material and prevent the electroplating solution from contacting the electrical contacts. 14 . The substrate of claim 12 , wherein increasing the rate at which the process region is plated is defined by increasing the applied electrical current while the electroplating solution is applied over the process region of the substrate, the thickness of the metallic material and resulting reduced electrical resistance facilitating increasing the applied electrical current. 15

Assignees

Inventors

Classifications

  • characterised by the construction of the load-lock chamber · CPC title

  • characterised by the construction of the transfer chamber · CPC title

  • by edge treatment, e.g. chamfering · CPC title

  • comprising at least one plating chamber · CPC title

  • of conductive or resistive materials · CPC title

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What does patent US2017330831A1 cover?
A substrate having at least one device; wherein the substrate having a conductive layer disposed on a top surface of the substrate, the top surface having an edge exclusion region defined as an annular area that extends to an edge of the substrate, the top surface of the substrate further having a process region defined as a central area of the substrate that extends to about the annular area; …
Who is the assignee on this patent?
Lam Res Corp
What technology area does this patent fall under?
Primary CPC classification H10W20/43. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Nov 16 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).