Vacuum-integrated hardmask processes and apparatus

Patent metadata

Field	Value
Publication number	US-9778561-B2
Application number	US-201514610038-A
Country	US
Kind code	B2
Filing date	Jan 30, 2015
Priority date	Jan 31, 2014
Publication date	Oct 3, 2017
Grant date	Oct 3, 2017

Abstract

Vacuum-integrated photoresist-less methods and apparatuses for forming metal hardmasks can provide sub-30 nm patterning resolution. A metal-containing (e.g., metal salt or organometallic compound) film that is sensitive to a patterning agent is deposited on a semiconductor substrate. The metal-containing film is then patterned directly (i.e., without the use of a photoresist) by exposure to the patterning agent in a vacuum ambient to form the metal mask. For example, the metal-containing film is photosensitive and the patterning is conducted using sub-30 nm wavelength optical lithography, such as EUV lithography.

First claim

What is claimed is:

1. A photoresist-less method of forming a metal mask, comprising:
depositing on a semiconductor substrate a EUV-sensitive metal-containing film of solid SnBr 4 having a thickness of between 5 and 200 nm;
patterning the metal-containing film with sub-30 nm resolution directly by EUV exposure having a wavelength in the range of 10 to 20 nm in a vacuum ambient; and
developing the pattern to form the metal mask.

2. The method of claim 1 , wherein the semiconductor substrate is a silicon wafer including partially-formed integrated circuits, and the method further comprising:
prior to the deposition, providing the semiconductor substrate in a first reactor chamber for the metal-containing film deposition; and
following the deposition, transferring the substrate under vacuum to a lithography processing chamber for the patterning.

3. The method of claim 2 , further comprising, prior to entering the lithography processing chamber, outgassing the substrate.

4. The method of claim 3 , wherein the outgassing comprises reducing the pressure surrounding the substrate to no more than 1E-8 Torr.

5. The method of claim 1 , further comprising pattern amplification by selective deposition on the metal mask.

6. The method of claim 5 , wherein the selective deposition comprises electroless deposition.

7. The method of claim 1 , wherein the EUV exposure has a wavelength of 13.5 nm.

8. The method of claim 1 , wherein the metal mask is formed on the substrate that is a silicon wafer including partially-formed integrated circuits.

9. The method of claim 1 , wherein the development of the pattern comprises heating the substrate to volatilize unexposed regions of the metal-containing film.

Assignees

• Lam Res Corp

Inventors

• Marks Jeffrey
• Antonelli George Andrew
• Gottscho Richard A
• Hausmann Dennis M
• Lavoie Adrien
• Knisley Thomas Joseph
• Reddy Sirish K
• Varadarajan Bhadri N
• Kolics Artur

Classifications

• H10P76/4085 Primary

  characterised by the processes involved to create the masks · CPC title

• H10P76/405 Primary

  characterised by their composition, e.g. multilayer masks · CPC title

• H10P72/0471

  comprising at least one ion or electron beam chamber · CPC title

• H10P72/0454

  surrounding a central transfer chamber · CPC title

• H10P72/0452

  characterised by the layout of the process chambers · CPC title