Vacuum-integrated hardmask processes and apparatus

US10831096B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10831096-B2
Application numberUS-201816206959-A
CountryUS
Kind codeB2
Filing dateNov 30, 2018
Priority dateJan 31, 2014
Publication dateNov 10, 2020
Grant dateNov 10, 2020

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Vacuum-integrated photoresist-less methods and apparatuses for forming metal hardmasks can provide sub-30 nm patterning resolution. A metal-containing (e.g., metal salt or organometallic compound) film that is sensitive to a patterning agent is deposited on a semiconductor substrate. The metal-containing film is then patterned directly (i.e., without the use of a photoresist) by exposure to the patterning agent in a vacuum ambient to form the metal mask. For example, the metal-containing film is photosensitive and the patterning is conducted using sub-30 nm wavelength optical lithography, such as EUV lithography.

First claim

Opening claim text (preview).

What is claimed is: 1. A photoresist-less method of forming a metal mask, comprising: depositing by condensation on a semiconductor substrate an EUV-sensitive metal-containing solid film selected from the group consisting of Sn(CH 3 ) 4 with a thickness of between 5 and 200 Å, and crystalline HfCl 4 with a thickness of between 50 and 2000 nm; patterning the metal-containing film with sub-30 nm resolution directly by EUV exposure having a wavelength in the range of 10 to 20 nm in a vacuum ambient; and developing the pattern to form the metal mask. 2. The method of claim 1 , wherein the semiconductor substrate is a silicon wafer including partially-formed integrated circuits, and the method further comprising: prior to the deposition, providing the semiconductor substrate in a first reactor chamber for the metal-containing film deposition; and following the deposition, transferring the substrate under vacuum to a lithography processing chamber for the patterning. 3. The method of claim 2 , further comprising, prior to entering the lithography processing chamber, outgassing the substrate. 4. The method of claim 3 , wherein the outgassing comprises reducing the pressure surrounding the substrate to no more than 1E-8 Torr. 5. The method of claim 1 , further comprising pattern amplification by selective deposition on the metal mask. 6. The method of claim 5 , wherein the selective deposition comprises electroless deposition. 7. The method of claim 1 , wherein the EUV exposure has a wavelength of 13.5 nm. 8. The method of claim 1 , wherein the metal mask is formed on the substrate that is a silicon wafer including partially-formed integrated circuits. 9. The method of claim 1 , wherein the development of the pattern comprises heating the substrate to volatilize unexposed regions of the metal-containing film. 10. The method of claim 1 , wherein the solid film is the Sn(CH 3 ) 4 and is deposited at a temperature of about 20° C. at a reactor pressure of less than 20 Torr. 11. The method of claim 10 , wherein the solid film is deposited to the thickness of 100 Å with the reactor pressure maintained at about 1 Torr. 12. The method of claim 10 , wherein the patterning involves the following decomposition chemistry: Sn(CH 3 ) 4 →Sn+2C 2 H 6 . 13. The method of claim 1 , wherein the solid film is the crystalline HfCl 4 and is deposited at a temperature of between 0 and 300° C. at a reactor pressure of less than 10 Torr. 14. The method of claim 13 , wherein the solid film is deposited to the thickness of 1000 nm with the reactor pressure maintained between 0.1 and 1 Torr and the temperature at 100° C. 15. The method of claim 13 , wherein the patterning involves the following decomposition chemistry: HfCl 4 →Hf+2Cl 2 . 16. A photoresist-less method of forming a metal mask, comprising: depositing by condensation on a semiconductor substrate an EUV-sensitive metal-containing solid film of SnBr 4 having a thickness of between 5 and 200 nm, wherein the solid film is deposited at a temperature between about 0 and 30° C. at a reactor pressure of less than 20 Torr; patterning the metal-containing film with sub-30 nm resolution directly by EUV exposure having a wavelength in the range of 10 to 20 nm in a vacuum ambient; and developing the pattern to form the metal mask. 17. The method of claim 16 , wherein the solid film is deposited to the thickness of 10 nm with the reactor pressure maintained between 14 and 15 Torr, and the temperature at 20° C. 18. The method of claim 16 , wherein the patterning involves the following decomposition chemistry: SnBr 4 →Sn+2Br 2 .

Assignees

Inventors

Classifications

  • characterised by the processes involved to create the masks · CPC title

  • H10P76/405Primary

    characterised by their composition, e.g. multilayer masks · CPC title

  • comprising at least one ion or electron beam chamber · CPC title

  • surrounding a central transfer chamber · CPC title

  • characterised by the layout of the process chambers · CPC title

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What does patent US10831096B2 cover?
Vacuum-integrated photoresist-less methods and apparatuses for forming metal hardmasks can provide sub-30 nm patterning resolution. A metal-containing (e.g., metal salt or organometallic compound) film that is sensitive to a patterning agent is deposited on a semiconductor substrate. The metal-containing film is then patterned directly (i.e., without the use of a photoresist) by exposure to the…
Who is the assignee on this patent?
Lam Res Corp
What technology area does this patent fall under?
Primary CPC classification H10P76/4085. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 10 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).