Interlevel conductor pre-fill utilizing selective barrier deposition

Patent metadata

Field	Value
Publication number	US-10262943-B2
Application number	US-201815877751-A
Country	US
Kind code	B2
Filing date	Jan 23, 2018
Priority date	Oct 25, 2014
Publication date	Apr 16, 2019
Grant date	Apr 16, 2019

Abstract

A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate having at least one dual damascene structure formed within a dielectric material over the substrate, the at least one dual damascene structure including a trench region and a vertical connection region formed to extend from a bottom of the trench region to an underlying conductive material such that the underlying conductive material is exposed at a bottom of the vertical connection region;
a self-assembled monolayer of an amino group formed on each sidewall of the vertical connection region without covering the underlying conductive material exposed at the bottom of the vertical connection region, the self-assembled monolayer also formed on each sidewall of the trench region and on the bottom of the trench region; and
a metallic material deposited to fill the vertical connection region in a bottom-to-top manner from the underlying conductive material exposed at the bottom of the vertical connection region to the bottom of the trench region;
a the barrier material disposed to cover the self-assembled monolayer on each sidewall of the trench region, the barrier material disposed to cover the self-assembled monolayer on the bottom of the trench region, and the barrier material disposed to cover the metallic material within the vertical connection region;
a liner material disposed to cover the barrier material, the liner material being different than the barrier material; and
an electrically conductive material disposed over the liner material to fill a remainder of the trench region.

2. The semiconductor device as recited in claim 1 , wherein the metallic material is deposited by an electroless deposition process to fill the vertical connection region.

3. The semiconductor device as recited in claim 2 , wherein the electroless deposition process initiates on the underlying conductive material exposed at the bottom of the vertical connection region.

4. The semiconductor device as recited in claim 1 , wherein the self-assembled monolayer is formed of an amidogen radical (NH 2 ).

5. The semiconductor device as recited in claim 1 , wherein the at least one dual damascene structure is exposed to fluid including 3-aminopropyltrimethoxysilane (APTMS) to form the self-assembled monolayer of the amino group on each sidewall of the vertical connection region.

6. The semiconductor device as recited in claim 5 , wherein the fluid includes APTMS in toluene, and wherein the fluid is in either a solution form or a vapor form.

7. The semiconductor device as recited in claim 1 , wherein the self-assembled monolayer of the amino group has a thickness of about 1 nanometer on each sidewall of the vertical connection region.

8. The semiconductor device as recited in claim 1 , wherein the dielectric material is a low-k dielectric material.

9. The semiconductor device as recited in claim 1 , wherein a ratio of a height of the vertical connection region to a width of the vertical connection region defines an aspect ratio of the vertical connection region, and wherein the aspect ratio of the vertical connection region is within a range extending from 1 to 60.

10. The semiconductor device as recited in claim 1 , wherein the vertical connection region is either cylindrically shaped or rectilinearly shaped.

11. The semiconductor device as recited in claim 1 , wherein the self-assembled monolayer of the amino group is formulated to selectively form on the dielectric material rather than on the underlying conductive material exposed at the bottom of the vertical connection region.

12. The semiconductor device as recited in claim 1 , wherein the metallic material is one or more of cobalt, copper, and nickel.

13. The semiconductor device as recited in claim 1 , wherein the underlying conductive material exposed at the bottom of the vertical connection region and the metallic material are a same material.

14. The semiconductor device as recited in claim 1 , wherein the underlying conductive material exposed at the bottom of the vertical connection region and the metallic material are different materials.

15. The semiconductor device as recited in claim 1 , wherein the self-assembled monolayer of the amino group is formulated to block diffusion of the metallic material through the self-assembled monolayer of the amino group and into the dielectric material.

16. The semiconductor device as recited in claim 1 , wherein the barrier material is tantalum nitride.

17. The semiconductor device as recited in claim 1 , wherein the liner material is tantalum or cobalt or ruthenium.

18. The semiconductor device as recited in claim 1 , wherein the electrically conductive material is copper.

19. The semiconductor device as recited in claim 1 , wherein the electrically conductive material is planarized to have a substantially planar top surface at a top of the trench region.

Assignees

• Lam Res Corp

Inventors

• Kolics Artur
• Lee William T
• Zhao Larry
• Wong Derek
• Nalla Praveen
• Ashtiani Kaihan
• Van Cleemput Patrick A
• Dordi Yezdi

Classifications

• H10P70/234

  the processing being the formation of vias or contact holes · CPC title

• H10P14/418

  the conductive layers comprising transition metals · CPC title

• H10P14/47

  Electrolytic deposition, i.e. electroplating; Electroless plating · CPC title

• H10P14/46

  using a liquid · CPC title

• H10P14/44

  Physical vapour deposition [PVD] · CPC title