Interlevel conductor pre-fill utilizing selective barrier deposition

Patent metadata

Field	Value
Publication number	US-9583386-B2
Application number	US-201514874307-A
Country	US
Kind code	B2
Filing date	Oct 2, 2015
Priority date	Oct 25, 2014
Publication date	Feb 28, 2017
Grant date	Feb 28, 2017

Abstract

A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor device, comprising:
providing a substrate having at least one dual damascene structure formed within a dielectric material over the substrate, the at least one dual damascene structure including a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material such that the underlying conductive material is exposed at a bottom of the opening;
forming an amorphous carbon barrier layer on each sidewall of the opening without covering the underlying conductive material exposed at the bottom of the opening;
performing a cleaning process on the substrate, with structures formed thereon, to remove material residues left over from formation of the amorphous carbon barrier layer; and
performing an electroless deposition process to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench, wherein the electroless deposition process initiates on the underlying conductive material exposed at the bottom of the opening.

2. The method of claim 1 , wherein forming the amorphous carbon barrier layer on each sidewall of the opening includes exposing the at least one dual damascene structure to a deposition plasma.

3. The method of claim 2 , wherein the deposition plasma is formed from a deposition gas that includes a hydrocarbon and an oxygen free inert diluent.

4. The method of claim 2 , wherein forming the amorphous carbon barrier layer on each sidewall of the opening further includes exposing the amorphous carbon barrier layer to a conditioning plasma.

5. The method of claim 4 , wherein the conditioning plasma is formed from a conditioning gas that includes hydrogen and that is essentially free of any hydrocarbon compound.

6. The method of claim 1 , wherein forming the amorphous carbon barrier layer on each sidewall of the opening includes performing a plasma-enhanced chemical vapor deposition process, or performing a deposition process that utilizes an inductively-coupled plasma, or performing a deposition process that utilizes a capacitively-coupled plasma, or performing a deposition process that utilizes a transformer-coupled plasma, or performing a deposition process that utilizes a remotely generated plasma relative to the substrate.

7. The method of claim 1 , wherein the dielectric material is a low-k dielectric material.

8. The method of claim 1 , wherein a ratio of a height of the opening to a width of the opening defines an aspect ratio of the opening, and wherein the aspect ratio of the opening is within a range extending from 1 to 60.

9. The method of claim 1 , wherein the opening is either cylindrically shaped or rectilinearly shaped.

10. The method of claim 1 , wherein the amorphous carbon barrier layer selectively deposits on the dielectric material without depositing on the underlying conductive material exposed at the bottom of the opening.

11. The method of claim 1 , wherein forming the amorphous carbon barrier layer includes deposition of one or more of carbon+nitrogen and carbon+boron.

12. The method of claim 1 , wherein the metallic material is one or more of cobalt, copper, and nickel.

13. The method of claim 1 , wherein the underlying conductive material exposed at the bottom of the opening and the metallic material are a same material.

14. The method of claim 1 , wherein the underlying conductive material exposed at the bottom of the opening and the metallic material are different materials.

15. The method of claim 1 , wherein the amorphous carbon barrier layer prevents the metallic material from diffusing into the dielectric material.

16. The method of claim 1 , further comprising:
depositing a barrier material to cover exposed surfaces of the trench and the metallic material that fills the opening;
depositing a liner material to cover exposed surfaces of the barrier material;
depositing a copper seed layer to cover exposed surfaces of the liner material; and
filling a remainder of the trench with copper by performing either a copper electroplating process or a copper electroless deposition process.

17. The method of claim 16 , wherein the barrier material is tantalum nitride.

18. The method of claim 16 , wherein the barrier material is deposited through a physical vapor deposition process or a chemical vapor deposition process or an atomic layer deposition process.

19. The method of claim 16 , wherein the liner material is tantalum or cobalt or ruthenium.

20. The method of claim 16 , wherein the liner material is deposited through a physical vapor deposition process or a chemical vapor deposition process.

21. The method of claim 16 , further comprising:
performing a planarization process to remove copper deposited above a top level of the trench.

Assignees

• Lam Res Corp

Inventors

• Kolics Artur
• Lee William T
• Zhao Larry
• Wong Derek
• Nalla Praveen
• Ashtiani Kaihan
• Van Cleemput Patrick A
• Dordi Yezdi

Classifications

• H10P70/234

  the processing being the formation of vias or contact holes · CPC title

• H10P14/418

  the conductive layers comprising transition metals · CPC title

• H10P14/47

  Electrolytic deposition, i.e. electroplating; Electroless plating · CPC title

• H10P14/46

  using a liquid · CPC title

• H10P14/44

  Physical vapour deposition [PVD] · CPC title