Root monitoring on an FPGA using satellite ADCs
US-11709275-B2 · Jul 25, 2023 · US
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Jennings John K patents
Jennings John K is listed as an inventor on 32 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Jennings John K |
| Total patents | 32 |
| First publication | Jan 15, 2015 |
| Latest publication | Jul 25, 2023 |
Notable patents
Publications ranked by popularity score, then publication date.
Time-multiplexed distribution of analog signals
US-11271581-B1 · Mar 8, 2022 · US
Device monitoring using satellite ADCS having local voltage reference
US-11199581-B1 · Dec 14, 2021 · US
Bias current variation correction for complementary metal-oxide-semiconductor (CMOS) temperature sensor
US-11181426-B1 · Nov 23, 2021 · US
Electro-static discharge (ESD) damage self-test
US-11177654-B1 · Nov 16, 2021 · US
Thermal load balancing of programmable devices
US-11012072-B1 · May 18, 2021 · US
Root monitoring on an fpga using satellite adcs
US-2021011172-A1 · Jan 14, 2021 · US
Capacitor-enhanced comparator for switched-capacitor (SC) circuits with reduced kickback
US-10756748-B1 · Aug 25, 2020 · US
Device monitoring using satellite ADCs having local capacitors
US-10705144-B1 · Jul 7, 2020 · US
Method of increased supply rejection on single-ended complementary metal-oxide-semiconductor (CMOS) switches
US-10608630-B1 · Mar 31, 2020 · US
Recent patents
Latest publications not already listed above.
Device monitoring using satellite ADCs having local voltage reference
US-10598729-B1 · Mar 24, 2020 · US
Dynamic element matching in an integrated circuit
US-10545053-B2 · Jan 28, 2020 · US
In-die transistor characterization in an IC
US-10379155-B2 · Aug 13, 2019 · US
Programmable temperature coefficient analog second-order curvature compensated voltage reference
US-2019172504-A1 · Jun 6, 2019 · US
Configurable single event latch-up (SEL) and electrical overvoltage stress (EOS) detection circuit
US-10289178-B1 · May 14, 2019 · US
Programmable temperature coefficient analog second-order curvature compensated voltage reference
US-10290330-B1 · May 14, 2019 · US
Self-biased operational transconductance amplifier-based reference circuit
US-10243526-B1 · Mar 26, 2019 · US
Analog switch having reduced gate-induced drain leakage
US-10236873-B2 · Mar 19, 2019 · US
Circuit for and method of implementing a multifunction output generator
US-10224884-B2 · Mar 5, 2019 · US
Dynamic element matching in an integrated circuit
US-2018356294-A1 · Dec 13, 2018 · US
Trim techniques for voltage reference circuits
US-10120399-B1 · Nov 6, 2018 · US
Area-efficient high-accuracy bandgap voltage reference circuit
US-10054968-B2 · Aug 21, 2018 · US
Circuit for and method of implementing a multifunction output generator
US-2018226929-A1 · Aug 9, 2018 · US
Area-efficient high-accuracy bandgap voltage reference circuit
US-2018074533-A1 · Mar 15, 2018 · US
Mitigation of single event latchup
US-9793899-B1 · Oct 17, 2017 · US
On chip detection of electrical overstress events
US-9575111-B1 · Feb 21, 2017 · US
Relaxation oscillator
US-9503058-B1 · Nov 22, 2016 · US
Analog switch having reduced gate-induced drain leakage
US-2016277019-A1 · Sep 22, 2016 · US
In-die transistor characterization in an ic
US-2016097805-A1 · Apr 7, 2016 · US
Switch supporting voltages greater than supply
US-9245886-B2 · Jan 26, 2016 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Xilinx Inc | 33 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G01K7/01 | 7 |
| H03K2217/0054 | 5 |
| G05F1/468 | 4 |
| G05F3/30 | 4 |
| G01K7/015 | 4 |