Electro-static discharge (ESD) damage self-test

US11177654B1 · US · B1

Patent metadata
FieldValue
Publication numberUS-11177654-B1
Application numberUS-201816152011-A
CountryUS
Kind codeB1
Filing dateOct 4, 2018
Priority dateOct 4, 2018
Publication dateNov 16, 2021
Grant dateNov 16, 2021

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

Examples described herein provide a circuit and methods for self-testing to detect damage to a device, which damage may be caused by an Electro-Static Discharge (ESD) event. In an example, an integrated circuit includes an input/output circuit, an ESD protection circuit, and a system monitor. The input/output circuit has an input/output node. The ESD protection circuit is connected to the input/output node. The system monitor has a driving/measurement node selectively connectable to the input/output node. The system monitor is configured to drive and measure a voltage of the driving/measurement node. The system monitor is further configured to determine, based on driving and measuring the voltage of the driving/measurement node, whether a damaged device is present. The damaged device is in the input/output circuit or the ESD protection circuit.

First claim

Opening claim text (preview).

What is claimed is: 1. An integrated circuit comprising: an input/output circuit having an input/output node; an Electro-Static Discharge (ESD) protection circuit connected to the input/output node; and a system monitor having a driving/measurement node selectively connectable via a switch to the input/output node, the system monitor being configured to drive and measure a voltage of the driving/measurement node, the system monitor further being configured to determine, based on driving and measuring the voltage of the driving/measurement node, whether a damaged device is present, the damaged device being in the input/output circuit or the ESD protection circuit. 2. The integrated circuit of claim 1 , wherein the system monitor comprises a driver and an analog-to-digital converter (ADC), the driver being connected to the driving/measurement node and operable to drive the voltage, the ADC being connected to the driving/measurement node and operable to measure the voltage. 3. The integrated circuit of claim 1 wherein the switch is connected between the input/output node and the driving/measurement node, the system monitor being operable to control the switch to be in an open state or a closed state, the switch being operable to selectively connect the driving/measurement node to the input/output node. 4. The integrated circuit of claim 1 , wherein the system monitor is operable to: when the driving/measurement node is connected to the input/output node: drive the input/output node to a drive voltage; terminate driving the input/output node; and after a pre-determined amount of time has elapsed from terminating driving the input/output node, measure a measured voltage of the input/output node; and determine whether a difference between an earlier voltage of the input/output node and the measured voltage indicates whether the damaged device is present. 5. The integrated circuit of claim 4 , wherein the earlier voltage is the drive voltage, the system monitor being operable to measure the drive voltage of the input/output node while driving the input/output node. 6. The integrated circuit of claim 4 , wherein: the damaged device is indicated as present when a magnitude of the difference exceeds a specification; and the damaged device is indicated as not being present when the magnitude of the difference does not exceed the specification. 7. The integrated circuit of claim 1 , wherein the system monitor is operable to: while driving the voltage of the driving/measurement node: measure a first measured voltage of the driving/measurement node when the driving/measurement node is not connected to the input/output node; connect the driving/measurement node to the input/output node; and measure a second measured voltage of the driving/measurement node when the driving/measurement node is connected to the input/output node; and determine whether a difference between the first measured voltage and the second measured voltage indicates whether the damaged device is present. 8. A method of operating an integrated circuit, the method comprising: selectively connecting, using a switch, a driving/measurement node of a system monitor to an input/output node of an input/output circuit, an Electro-Static Discharge (ESD) protection circuit being connected to the input/output node; driving, using the system monitor, a voltage of the driving/measurement node, at least some of the driving being performed while the driving/measurement node is connected to the input/output node; determining, using the system monitor, a voltage difference between measured voltages of the driving/measurement node, the voltage difference being at least partially in response to driving the voltage of the driving/measurement node; determining, using the system monitor, whether the voltage difference indicates a presence of a damaged device, wherein the damaged device is in the input/output circuit or the ESD protection circuit; and storing in memory, using the system monitor, a result corresponding to whether the voltage difference indicates the presence of the damaged device. 9. The method of claim 8 further comprising outputting the result to a user device. 10. The method of claim 8 further comprising setting the input/output circuit to a high-impedance state. 11. The method of claim 8 , wherein the switch is controlled by the system monitor. 12. The method of claim 8 , wherein the system monitor comprises: a driver, wherein the driver is used to charge the driving/measurement node; and an analog-to-digital converter (ADC), wherein the ADC is used to measure the measured voltages of the driving/measurement node. 13. The method of claim 8 , wherein: determining the voltage difference between the measured voltages of the driving/measurement node includes: driving the voltage of the driving/measurement node when the driving/measurement node is connected to the input/output node; terminating driving the voltage of the driving/measurement node; and after a pre-determined amount of time has elapsed from terminating driving the voltage of the driving/measurement node, measuring a subsequent measured voltage of the driving/measurement node when the driving/measurement node is connected to the input/output node, wherein the voltage difference is between an earlier measured voltage of the driving/measurement node and the subsequent measured voltage; and determining whether the voltage difference indicates the presence of the damaged device includes comparing the voltage difference to a specification, wherein the presence of the damaged device is indicated when a magnitude of the voltage difference exceeds the specification. 14. The method of claim 13 , wherein determining the voltage difference between the measured voltages of the driving/measurement node includes: measuring the earlier measured voltage of the driving/measurement node when driving the voltage of the driving/measurement node and the driving/measurement node is connected to the input/output node. 15. The method of claim 8 , wherein: determining the voltage difference between the measured voltages of the driving/measurement node includes: driving the voltage of the driving/measurement node when the driving/measurement node is not connected to the input/output node; measuring a first measured voltage of the driving/measurement node when the driving/measurement node is not connected to the input/output node and while driving the voltage of the driving/measurement node; and measuring a second measured voltage of the driving/measurement node when the driving/measurement node is connected to the input/output node and while driving the voltage of the driving/measurement node, wherein the voltage difference is between the first measured voltage and the second measured voltage; and determining whether the voltage difference indicates the presence of the damaged device includes comparing the voltage difference to a specification, wherein the presence of the damaged device is indicated when a magnitude of the voltage difference exceeds the specification. 16. An integrated circuit comprising: an input/output circuit having an input/output node; an Electro-Static Discharge (ESD) protection circuit connected to the input/output node; and a system monitor having a driving/measurement node selectively connectable via a switch to the input/output node, the system monitor comprising: a driver configured to drive a voltage of the driving/measurement node; an analog-to-digital converter (ADC) configured to obtain measurement data relating to the driv

Assignees

Inventors

Classifications

  • Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] · CPC title

  • using FETs as protective elements · CPC title

  • H02H9/046Primary

    responsive to excess voltage appearing at terminals of integrated circuits · CPC title

  • H02H9/042Primary

    comprising means to limit the absorbed power or indicate damaged over-voltage protection device · CPC title

  • concerning the detecting means (in general G01R or other subclasses of G01; reed switches H01H71/2445) · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US11177654B1 cover?
Examples described herein provide a circuit and methods for self-testing to detect damage to a device, which damage may be caused by an Electro-Static Discharge (ESD) event. In an example, an integrated circuit includes an input/output circuit, an ESD protection circuit, and a system monitor. The input/output circuit has an input/output node. The ESD protection circuit is connected to the input…
Who is the assignee on this patent?
Xilinx Inc
What technology area does this patent fall under?
Primary CPC classification H02H9/046. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 16 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).