Switch supporting voltages greater than supply

Patent metadata

Field	Value
Publication number	US-9245886-B2
Application number	US-201313941419-A
Country	US
Kind code	B2
Filing date	Jul 12, 2013
Priority date	Jul 12, 2013
Publication date	Jan 26, 2016
Grant date	Jan 26, 2016

Abstract

Devices for isolating an input from an output are disclosed. For example, a device includes a first p-type metal oxide semiconductor transistor and a first circuit. A source of the first p-type metal oxide semiconductor transistor is connected to an input of the device. The first circuit is for delivering a signal on the input of the device to a gate of the first p-type metal oxide semiconductor transistor when an enable signal is deactivated and for delivering a ground voltage to the gate of the first p-type metal oxide semiconductor transistor when the enable signal is activated.

First claim

What is claimed is:

1. A device, comprising:
a first p-type metal oxide semiconductor transistor, wherein a source of the first p-type metal oxide semiconductor transistor is connected to an input of the device; and
a first circuit, for delivering a signal on the input of the device to a gate of the first p-type metal oxide semiconductor transistor when an enable signal is deactivated and for delivering a ground voltage to the gate of the first p-type metal oxide semiconductor transistor when the enable signal is activated, wherein the first circuit comprises:
a second p-type metal oxide semiconductor transistor, wherein a source of the second p-type metal oxide semiconductor transistor is connected to the input of the device and wherein a gate of the second p-type metal oxide semiconductor transistor is connected to the enable signal;
a first n-type metal oxide semiconductor transistor, wherein a source of the first n-type metal oxide semiconductor transistor is connected to ground, wherein a drain of the first n-type metal oxide semiconductor transistor is connected to a drain of the second p-type metal oxide semiconductor transistor, wherein a gate of the first n-type metal oxide semiconductor transistor is connected to the enable signal; and
a second n-type metal oxide semiconductor transistor, wherein a gate of the second n-type metal oxide semiconductor transistor is connected to an inversion of the enable signal, wherein a source of the second n-type metal oxide semiconductor transistor is connected to the input of the device, and wherein the drain of the second p-type metal oxide semiconductor transistor, the drain of the first n-type metal oxide semiconductor transistor, and a drain of the second n-type metal oxide semiconductor transistor are connected to the gate of the first p-type metal oxide semiconductor transistor.

2. The device of claim 1 , wherein the source of the first p-type metal oxide semiconductor transistor is shorted to a bulk of the first p-type metal oxide semiconductor transistor.

3. The device of claim 1 , wherein the inversion of the enable signal and ground are a same voltage.

4. The device of claim 1 , further comprising:
a third p-type metal oxide semiconductor transistor, wherein a source of the third p-type metal oxide semiconductor transistor is connected to an output of the device, and wherein a drain of the third p-type metal oxide semiconductor transistor is connected to a drain of the first p-type metal oxide semiconductor transistor; and
a second circuit, for delivering a signal on the output of the device to a gate of the third p-type metal oxide semiconductor transistor when the enable signal is deactivated and for delivering the ground voltage to a gate of the third p-type metal oxide semiconductor transistor when the enable signal is activated.

5. The device of claim 4 , wherein the second circuit comprises:
a fourth p-type metal oxide semiconductor transistor, wherein a source of the fourth p-type metal oxide semiconductor transistor is connected to the output of the device and wherein a gate of the fourth p-type metal oxide semiconductor transistor is connected to the enable signal;
a third n-type metal oxide semiconductor transistor, wherein a source of the third n-type metal oxide semiconductor transistor is connected to ground and wherein a gate of the third n-type metal oxide semiconductor transistor is connected to the enable signal; and
a fourth n-type metal oxide semiconductor transistor, wherein a gate of the fourth n-type metal oxide semiconductor transistor is connected to an inversion of the enable signal, wherein a source of the fourth n-type metal oxide semiconductor transistor is connected to the output of the device, and wherein a drain of the fourth p-type metal oxide semiconductor transistor, a drain of the third n-type metal oxide semiconductor transistor, and a drain of the fourth n-type metal oxide semiconductor transistor are connected to the gate of the third p-type metal oxide semiconductor transistor.

6. The device of claim 1 , further comprising:
a fifth n-type metal oxide semiconductor transistor, wherein a source of the fifth n-type metal oxide semiconductor transistor is connected to the input of the device; and
a third circuit, for delivering a signal on the input of the device to a gate of the fifth n-type metal oxide semiconductor transistor when the enable signal is deactivated and for delivering a supply voltage to the gate of the fifth n-type metal oxide semiconductor transistor when the enable signal is activated.

7. The device of claim 6 , wherein the enable signal is a same voltage as the supply voltage.

8. The device of claim 6 , wherein the input of the device comprises an analog signal having a voltage between a voltage level of ground and a voltage level of the supply voltage.

9. The device of claim 6 , wherein the third circuit comprises:
a sixth n-type metal oxide semiconductor transistor, wherein a source of the sixth n-type metal oxide semiconductor transistor is connected to the input of the device and wherein a gate of the sixth n-type metal oxide semiconductor transistor is connected to the inversion of the enable signal;
a fifth p-type metal oxide semiconductor transistor, wherein a source of the fifth p-type metal oxide semiconductor transistor is connected to the supply voltage and wherein a gate of the fifth p-type metal oxide semiconductor transistor is connected to an inversion of the enable signal; and
a sixth p-type metal oxide semiconductor transistor, wherein a source of the sixth p-type metal oxide semiconductor transistor is connected to the input signal, wherein a gate of the sixth p-type metal oxide semiconductor transistor is connected to the enable signal, and wherein a drain of the sixth n-type metal oxide semiconductor transistor, a drain of the fifth p-type metal oxide semiconductor transistor and a drain of the sixth p-type metal oxide semiconductor transistor are connected to a gate of the fifth n-type metal oxide semiconductor transistor.

10. The device of claim 6 , further comprising:
a seventh n-type metal oxide semiconductor transistor, wherein a source of the seventh n-type metal oxide semiconductor transistor is connected to an output of the device and wherein a drain of the seventh n-type metal oxide semiconductor transistor is connected to a drain of the fifth n-type metal oxide semiconductor transistor; and
a fourth circuit, for delivering a signal on the output of the device to a gate of the seventh n-type metal oxide semiconductor transistor when the enable signal is deactivated and for delivering a supply voltage to the gate of the seventh n-type metal oxide semiconductor transistor when the enable signal is activated.

11. The device of claim 10 , wherein the fourth circuit comprises:
a seventh p-type metal oxide semiconductor transistor, wherein a source of the seventh p-type metal oxide semiconductor transistor is connected to the supply voltage and wherein a gate of the seventh p-type metal oxide semiconductor transistor is connected to the inversion of the enable signal;
an eighth n-type metal oxide semiconductor transistor, wherein a source of the eighth n-type metal oxide semiconductor transistor is connected to the output of the device and wherein a gate of the eighth n-type metal oxide semiconductor transistor is connected to the inversion of the enable signal; and
an eighth p-type metal oxide semiconductor transistor, wherein a source of the eighth p-type metal oxide semiconductor transistor is connected to the output of the device, wherein a gate of the eighth p-type metal oxide semiconductor transistor is connected to the enable signal, wherein

Assignees

• Xilinx Inc

Inventors

• Jennings John K
• Cical Ionut C

Classifications

• H10D84/85 Primary

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D30/60

  Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) · CPC title

• H01L27/092 Primary

  Electricity · mapped topic

• H03K2017/066

  Maximizing the OFF-resistance instead of minimizing the ON-resistance · CPC title

• H03K17/08122

  in field-effect transistor switches · CPC title