Dynamic element matching in an integrated circuit

Patent metadata

Field	Value
Publication number	US-10545053-B2
Application number	US-201715616765-A
Country	US
Kind code	B2
Filing date	Jun 7, 2017
Priority date	Jun 7, 2017
Publication date	Jan 28, 2020
Grant date	Jan 28, 2020

Abstract

An example dynamic element matching (DEM) circuit includes: a plurality of bipolar junction transistors (BJTs), each of the plurality of BJTs having a base terminal and a collector terminal coupled to electrical ground; a plurality of pairs of force switches, each pair of force switches coupled to an emitter of a respective one of the plurality of BJTs; a plurality of pairs of sense switches, where each pair of sense switches is coupled to the emitter of a respective one of the plurality of BJTs, a first switch in each pair of sense switches is coupled to a first node, and a second switch in each pair of sense switches is coupled to a second node; a first current source coupled to a first switch in each pair of force switches; and a second current source coupled to a second switch in each pair of force switches.

First claim

What is claimed is:

1. A dynamic element matching (DEM) circuit, comprising:
a plurality of bipolar junction transistors (BJTs), each of the plurality of BJTs having a base terminal and a collector terminal coupled to electrical ground;
a plurality of pairs of force switches, each pair of force switches coupled to an emitter of a respective one of the plurality of BJTs;
a plurality of pairs of sense switches, where each pair of sense switches is coupled to the emitter of a respective one of the plurality of BJTs, a first switch in each pair of sense switches is coupled to a first node, and a second switch in each pair of sense switches is coupled to a second node;
a first current source coupled to a first switch in each pair of force switches; and
a second current source coupled to a second switch in each pair of force switches.

2. The DEM circuit of claim 1 , wherein a first current supplied by the first current source and a second current supplied by the second current source is substantially the same.

3. The DEM circuit of claim 1 , wherein a first current supplied by the first current source is greater than a second current supplied by the second current source or the second current is greater than the first current.

4. The DEM circuit of claim 1 , further comprising:
a switch controller coupled to the plurality of pairs of force switches and the plurality of pairs of sense switches.

5. The DEM circuit of claim 4 , wherein the switch controller is configured to generate a plurality of differential logic signal pairs, where each pair of sense switches and each pair of force switches receives a respective one of the plurality of differential logic signal pairs.

6. The DEM circuit of claim 5 , wherein the first switch in each pair of the force switches receives a true logic signal of a respective differential logic signal pair and the second switch in each pair of the force switches receives a complement logic signal of the respective differential logic signal pair.

7. The DEM circuit of claim 6 , wherein the first switch in each pair of the sense switches receives the true logic signal of the respective differential logic signal pair and the second switch in each pair of the sense switches receives the complement logic signal of the respective differential logic signal pair.

8. An integrated circuit (IC), comprising:
a system monitor circuit; and
at least one dynamic element matching (DEM) circuit coupled to the system monitor circuit, each of the at least one DEM circuit comprising:
a plurality of bipolar junction transistors (BJTs), each of the plurality of BJTs having a base terminal and a collector terminal coupled to electrical ground;
a plurality of pairs of force switches, each pair of force switches coupled to an emitter of a respective one of the plurality of BJTs;
a plurality of pairs of sense switches, where each pair of sense switches is coupled to the emitter of a respective one of the plurality of BJTs, a first switch in each pair of sense switches is coupled to a first node, and a second switch in each pair of sense switches is coupled to a second node;
a first current source coupled to a first switch in each pair of force switches; and
a second current source coupled to a second switch in each pair of force switches.

9. The IC of claim 8 , wherein a first current supplied by the first current source and a second current supplied by the second current source is substantially the same.

10. The IC of claim 8 , wherein each of the at least one DEM circuit is a temperature sensing circuit.

11. The IC of claim 8 , further comprising:
a switch controller coupled to the plurality of pairs of force switches and the plurality of pairs of sense switches.

12. The IC of claim 11 , wherein the switch controller is configured to generate a plurality of differential logic signal pairs, where each pair of sense switches and each pair of force switches receives a respective one of the plurality of differential logic signal pairs.

13. The IC of claim 12 , wherein the first switch in each pair of the force switches receives a true logic signal of a respective differential logic signal pair and the second switch in each pair of the force switches receives a complement logic signal of the respective differential logic signal pair.

14. The IC of claim 13 , wherein the first switch in each pair of the sense switches receives the true logic signal of the respective differential logic signal pair and the second switch in each pair of the sense switches receives the complement logic signal of the respective differential logic signal pair.

Assignees

• Xilinx Inc

Inventors

• Kamath Umanath R
• Kelly Padraig
• Jennings John K

Classifications

• G01K7/015

  using microstructures, e.g. made of silicon · CPC title

• G01K1/026 Primary

  arrangements for monitoring a plurality of temperatures, e.g. by multiplexing · CPC title

• H03K19/00307 Primary

  in bipolar transistor circuits · CPC title

• G01K7/01 Primary

  using semiconducting elements having PN junctions (G01K7/02, G01K7/16, G01K7/30 take precedence) · CPC title

• H03K19/017581

  programmable · CPC title