Capacitor-enhanced comparator for switched-capacitor (SC) circuits with reduced kickback

Patent metadata

Field	Value
Publication number	US-10756748-B1
Application number	US-201916396257-A
Country	US
Kind code	B1
Filing date	Apr 26, 2019
Priority date	Apr 26, 2019
Publication date	Aug 25, 2020
Grant date	Aug 25, 2020

Abstract

Apparatus and associated methods relate to a circuit that is configured to keep a comparator input voltage stable. In an illustrative example, the circuit may include a first differential path coupled to a first switched-capacitor network's output, a second differential path coupled to a second switched-capacitor network's output. A comparator may have a first input coupled to the first differential path and a second input coupled to the second differential path. The comparator may be controlled by a clock signal to perform comparison. A first capacitor may be coupled from the clock signal to the first differential signal path and a second capacitor may be coupled from the clock signal to the second differential signal path. By introducing the first capacitor and the second capacitor, the comparator input common-mode may keep stable, and the comparator may be less sensitive to kickback effects.

First claim

What is claimed is:

1. A circuit, comprising:
a first differential path coupled to an output of a first switched-capacitor network that is configured to receive a first differential input;
a second differential path coupled to an output of a second switched-capacitor network that is configured to receive a second differential input;
a comparator circuit having a first input coupled to the first differential path and a second input coupled to the second differential path, wherein the comparator circuit is configured to enable comparison between the first differential path and the second differential path in response to a clock signal;
a first capacitor coupled from the clock signal to the first differential signal path;
a second capacitor coupled from the clock signal to the second differential signal path;
a third capacitor coupled from a common mode voltage of the comparator circuit to the first differential signal path; and,
a fourth capacitor coupled from the common mode voltage of the comparator circuit to the second differential signal path,
wherein the first differential path comprises a first pre-amplifier circuit having an input coupled to the third capacitor, and an output coupled to the first capacitor, the second differential path comprises a second pre-amplifier circuit having an input coupled to the fourth capacitor, and an output coupled to the second capacitor.

2. The circuit of claim 1 , wherein the third capacitor is a metal-oxide-metal capacitor.

3. The circuit of claim 2 , wherein the fourth capacitor is a metal-oxide-metal capacitor.

4. The circuit of claim 1 , wherein the third capacitor is a metal-insulator-metal (MIM) capacitor.

5. The circuit of claim 4 , wherein the fourth capacitor is a metal-insulator-metal (MIM) capacitor.

6. The circuit of claim 1 , wherein the first capacitor is a metal-insulator-metal capacitor.

7. The circuit of claim 6 , wherein the second capacitor is a metal-insulator-metal capacitor.

8. An analog-to-digital converter (ADC), comprising:
a first switched-capacitor network having an input configured to receive a first differential input and an output coupled to a first differential path;
a second switched-capacitor network having an input configured to receive a second differential input and an output coupled to a second differential path;
a comparator circuit having a first input coupled to an output of the first differential path and a second input coupled to an output of the second differential path, wherein the comparator circuit is configured to enable comparison between the first differential path and the second differential path in response to a clock signal;
a first capacitor coupled from the clock signal to the first differential signal path;
a second capacitor coupled from the clock signal to the second differential signal path;
a third capacitor coupled from a common mode voltage of the comparator circuit to the first differential signal path; and,
a fourth capacitor coupled from the common mode voltage of the comparator circuit to the second differential signal path,
wherein the first differential path comprises a first pre-amplifier having an input coupled to the third capacitor, and an output coupled to the first capacitor, the second differential path comprises a second pre-amplifier having an input coupled to the fourth capacitor, and an output coupled to the second capacitor.

9. The ADC of claim 8 , wherein the third capacitor is a metal-oxide-metal capacitor.

10. The ADC of claim 9 , wherein the fourth capacitor is a metal-oxide-metal capacitor.

11. The ADC of claim 8 , wherein the ADC is a successive approximation register (SAR) ADC.

12. A method, comprising:
providing a first differential path, wherein the first differential path is coupled to an output of a first switched-capacitor network that is configured to receive a first differential input;
providing a second differential path, wherein the second differential path is coupled to an output of a second switched-capacitor network that is configured to receive a second differential input;
providing a comparator circuit with a first input coupled to the first differential path and a second input coupled to the second differential path, wherein the comparator circuit is configured to enable comparison between the first differential path and the second differential path in response to a clock signal;
providing a first capacitor, wherein the first capacitor is coupled from the clock signal to the first differential signal path;
providing a second capacitor, wherein the second capacitor is coupled from the clock signal to the second differential signal path;
coupling a third capacitor from a common mode voltage of the comparator circuit to the first differential signal path;
coupling a fourth capacitor from the common mode voltage of the comparator circuit to the second differential signal path;
providing a first pre-amplifier circuit with an input coupled to the third capacitor, and an output coupled to the first capacitor; and,
providing a second pre-amplifier circuit with an input coupled to the fourth capacitor, and an output coupled to the second capacitor.

13. The method of claim 12 , wherein the third capacitor is a metal-oxide-metal capacitor.

14. The method of claim 13 , wherein the fourth capacitor is a metal-oxide-metal capacitor.

Assignees

• Xilinx Inc

Inventors

• Khatavkar Prathamesh M
• Jennings John K
• Morgado Alonso

Classifications

• H10D1/692

  Electrodes · CPC title

• H10D1/66

  Conductor-insulator-semiconductor capacitors, e.g. MOS capacitors · CPC title

• H03H19/004

  Switched capacitor networks · CPC title

• H03K5/2481 Primary

  with at least one differential stage · CPC title

• H03M1/466 Primary

  using switched capacitors · CPC title