Thermal load balancing of programmable devices

Patent metadata

Field	Value
Publication number	US-11012072-B1
Application number	US-202016749707-A
Country	US
Kind code	B1
Filing date	Jan 22, 2020
Priority date	Jan 22, 2020
Publication date	May 18, 2021
Grant date	May 18, 2021

Abstract

Method and apparatus for monitoring and reconfiguring a programmable device are disclosed. In some implementations, the programmable device may include a processor and a plurality of satellite monitors to determine operating temperatures at various locations throughout the programmable device. When temperatures of at least some of the satellite monitors exceed a threshold, the processor may reconfigure the programmable device using an alternative configuration. The alternative configuration may provide equivalent functionality with respect to an initial configuration through a different arrangement of functional blocks within the programmable device. The new arrangement of functional blocks may reduce operating temperatures by relocating blocks to different regions of the programmable device.

First claim

What is claimed is:

1. A method for operating a field programmable gate array (FPGA), comprising:
determining, by a plurality of temperature sensors, a temperature associated with one or more regions of the FPGA;
determining an alternative configuration for the FPGA based on the temperature associated with the one or more regions; and
relocating functions performed by one or more first programmable regions of the FPGA to one or more second programmable regions of the FPGA based on the alternative configuration.

2. The method of claim 1 , wherein the determining of the alternative configuration is performed in response to determining that a temperature associated with at least one region of the FPGA is greater than a temperature threshold.

3. The method of claim 2 , wherein the temperature threshold associated with a first region of the FPGA is different from the temperature threshold associated with a second region of the FPGA.

4. The method of claim 1 , wherein the determined alternative configuration is selected from a plurality of configuration files provided by a user.

5. The method of claim 1 , wherein the FPGA is a system-on-a chip (SoC) device comprising:
one or more scalar engines for performing numeric and procedural processing tasks;
one or more adaptable engines for implementing programmable logic designs; and
one or more intelligent engines for performing inference processing and machine learning tasks.

6. The method of claim 1 , wherein the determined alternative configuration partially reconfigures the FPGA.

7. The method of claim 1 , wherein the relocating comprises:
dynamically relocating the functions performed by the one or more first programmable regions while the FPGA is operating in accordance with another configuration.

8. The method of claim 1 , wherein determining the alternative configuration further comprises generating, by the FPGA, a configuration bitstream.

9. The method of claim 1 , wherein a plurality of alternative configuration files describing one or more alternative configurations are stored within the FPGA.

10. A field programmable gate array (FPGA) comprising:
a plurality of programmable regions, wherein each programmable region is configured to perform one or more functions; and
a platform management controller coupled to the plurality of programmable regions and configured to:
determine a temperature associated with one or more regions of the FPGA;
determine an alternative configuration for the FPGA based on the temperature associated with the one or more regions; and
relocate functions performed by one or more first programmable regions to one or more second programmable regions based on the alternative configuration.

11. The FPGA of claim 10 , wherein the determination of the alternative configuration is performed in response to a determination that a temperature associated with at least one region of the FPGA is greater than a temperature threshold.

12. The FPGA of claim 11 , wherein the temperature threshold associated with a first region of the FPGA is different from the temperature threshold associated with a second region of the FPGA.

13. The FPGA of claim 10 , wherein the platform management controller is further configured to select the alternative configuration from a plurality of configuration files provided by a user.

14. The FPGA of claim 10 , comprising:
one or more scalar engines configured to perform numeric and procedural tasks;
one or more adaptable engines configured to implement programmable logic designs; and
one or more intelligent engines configured to perform inference processing and machine learning tasks.

15. The FPGA of claim 10 , wherein the alternative configuration is to partially reconfigure the FPGA.

16. The FPGA of claim 10 , wherein the platform management controller is further configured to dynamically relocate the functions performed by the one or more first programmable regions while the FPGA is operating in accordance with another configuration.

17. The FPGA of claim 10 , wherein the platform management controller is further configured to generate a configuration bitstream based at least in part on the alternative configuration.

18. The FPGA of claim 10 , wherein a plurality of alternative configuration files are stored within the FPGA.

19. The FPGA of claim 10 , wherein the FPGA further comprises a plurality of temperature sensors, each of the temperature sensors being configured to determine the temperature associated with a respective one of the one or more regions of the FPGA.

20. A field programmable gate array (FPGA) comprising:
means for determining a temperature associated with one or more regions of the FPGA;
means for determining an alternative configuration for the FPGA based on the temperature associated with the one or more regions; and
means for relocating functions performed by one or more first programmable regions of the FPGA to one or more second programmable regions of the FPGA based on the alternative configuration.

Assignees

• Xilinx Inc

Inventors

• Jennings John K
• Farley Brendan

Classifications

• H03K19/00369 Primary

  Modifications for compensating variations of temperature, supply voltage or other physical parameters · CPC title

• H03K19/17708 Primary

  using an AND matrix followed by an OR matrix, i.e. programmable logic arrays · CPC title