On chip detection of electrical overstress events

Patent metadata

Field	Value
Publication number	US-9575111-B1
Application number	US-201313942626-A
Country	US
Kind code	B1
Filing date	Jul 15, 2013
Priority date	Jul 15, 2013
Publication date	Feb 21, 2017
Grant date	Feb 21, 2017

Abstract

A system configured for detecting electrical overstress events within an integrated circuit includes a comparator configured to determine whether a monitored voltage level of a monitored signal exceeds an overstress reference voltage level. The overstress reference voltage level is a predetermined amount of voltage above a nominal voltage level for the monitored signal. The system further includes a write circuit coupled to an output of the comparator. The write circuit is configured to indicate an occurrence of an electrical overstress event within the integrated circuit responsive to the comparator determining that the monitored voltage level exceeds the overstress reference voltage level.

First claim

What is claimed is:

1. A system implemented within an integrated circuit, the system comprising:
a first comparator configured to determine whether a monitored voltage level of a first monitored signal exceeds an overstress reference signal;
a second comparator configured to determine whether the monitored voltage level of a second monitored signal exceeds the overstress reference signal;
wherein the overstress reference signal is a predetermined amount of voltage above a nominal voltage level for one of the first and second monitored signals;
a write circuit coupled to an output of the first and the second comparators;
wherein the write circuit is configured to indicate a first occurrence of an electrical overstress event and a second occurrence of the electrical overstressed event within the integrated circuit responsive to the first and the second comparators determining that the monitored voltage levels of the first and second monitored signals exceed the overstress reference signal; and
a non-volatile memory coupled to the write circuit;
wherein the write circuit is configured to indicate the first occurrence of an electrical overstress event and the second occurrence of an electrical overstress event by storing a first indication and a second indication of the overstress events within the non-volatile memory.

2. The system of claim 1 , wherein:
the non-volatile memory comprises a one-time programmable memory cell; and
wherein the write circuit stores the indicator by programming the one-time programmable memory cell.

3. The system of claim 1 , wherein:
the write circuit is coupled to an output pin of the integrated circuit; and
the write circuit indicates occurrences of the electrical overstress events within the integrated circuit by outputting indicators from the integrated circuit through the output pin.

4. The system of claim 1 , wherein:
the first and the second comparators receive the first monitored signal at a first input;
the first and the second comparators receive a reference signal at the overstress reference signal at a second input; and
the first and the second comparators compare the monitored first and second signals with the reference signal.

5. The system of claim 4 , wherein:
the reference signal is provided from a battery source; and
the battery source provides power to the first comparator, the second comparator and the write circuit.

6. The system of claim 1 , wherein:
the first comparator receives, at a first input, a version of the first monitored signal;
wherein the version of the first monitored signal has a voltage level that is the monitored voltage level reduced by a voltage drop from at least one diode;
the first comparator receives, at a second input, a reference signal;
wherein the reference signal has a voltage level that is the overstress reference signal reduced by an amount of voltage equal to the voltage drop; and
the first comparator compares the version of the first monitored signal with the reference signal.

7. The system of claim 1 , wherein:
the second comparator receives, at a first input, a version of the monitored signal;
wherein the version of the second monitored signal has a voltage level that is the monitored voltage level reduced by a voltage drop from at least one diode;
the second comparator receives, at a second input, a reference signal;
wherein the reference signal has a voltage level that is the overstress reference signal reduced by an amount of voltage equal to the voltage drop; and
the second comparator compares the version of the second monitored signal with the reference signal.

8. The system of claim 6 , wherein:
the first monitored signal is coupled to an anode of a first diode of a plurality of diodes;
the plurality of diodes are serially connected;
a cathode of a last diode of the plurality of diodes is coupled to ground;
a first input of the first comparator is coupled to a first and second nodes between two consecutive diodes of the plurality of diodes; and
the nodes generate a version of the first monitored signal.

9. The system of claim 7 , wherein:
the second monitored signal is coupled to an anode of a first diode of a plurality of diodes;
the plurality of diodes are serially connected;
a cathode of a last diode of the plurality of diodes is coupled to ground;
a first input of the second comparators is coupled to a first and second nodes between two consecutive diodes of the plurality of diodes; and
the nodes generate versions of the monitored signal.

10. The system of claim 1 , further comprising:
first and second drivers having inputs and outputs;
wherein an input of the first and the second drivers are coupled to outputs of the first and the second comparators, and outputs of the first and second drivers are coupled to inputs of the write circuitry; and
the first and second capacitors are coupled between the output of the first and the at least second comparators and ground.

Assignees

• Xilinx Inc

Inventors

• Karp James
• Hart Michael J
• Jennings John K

Classifications

• H02H3/20

  responsive to excess voltage · CPC title

• G01R31/26 Primary

  Testing of individual semiconductor devices (testing of photovoltaic devices H02S50/10; testing or measuring during manufacture or treatment {H10P74/00}) · CPC title

• H03K17/08 Primary

  Modifications for protecting switching circuit against overcurrent or overvoltage · CPC title

• H02H3/00

  Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection (specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems H02H7/00; systems for change-over to standby supply H02J9/00 ){; integrated protection (for motors H02H7/0822)} · CPC title

• H03K19/00369 Primary

  Modifications for compensating variations of temperature, supply voltage or other physical parameters · CPC title