Area-efficient high-accuracy bandgap voltage reference circuit

Patent metadata

Field	Value
Publication number	US-10054968-B2
Application number	US-201615266947-A
Country	US
Kind code	B2
Filing date	Sep 15, 2016
Priority date	Sep 15, 2016
Publication date	Aug 21, 2018
Grant date	Aug 21, 2018

Abstract

An integrated circuit includes a reference voltage circuit. The reference voltage circuit includes a bipolar junction transistor (BJT) configured to receive a first current during a first phase of a clock cycle to generate a first base-emitter junction voltage, and receive a second current during a second phase of the clock cycle to generate a second base-emitter junction voltage. The reference voltage circuit includes a switched capacitor circuit configured to provide a reference voltage associated with the first base-emitter junction voltage and the second base-emitter junction voltage.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a reference voltage circuit including:
a bipolar junction transistor (BJT) configured to:
receive a first current during a first phase of a clock cycle to generate a first base-emitter junction voltage; and
receive a second current during a second phase of the clock cycle to generate a second base-emitter junction voltage; and

a switched capacitor circuit configured to provide a reference voltage associated with the first base-emitter junction voltage and the second base-emitter junction voltage.

2. The integrated circuit of claim 1 , wherein the reference voltage circuit is coupled to a supply voltage less than about 1.5 volts.

3. The integrated circuit of claim 1 , wherein the reference voltage circuit includes:
an operational amplifier having a first input, a second input, and an output,
wherein the first input of the operational amplifier is coupled to the first capacitor,
wherein the second input of the operational amplifier is coupled to the second capacitor, and
wherein the output of the operational amplifier provides the reference voltage.

4. The integrated circuit of claim 1 , wherein the reference voltage is equal to or less than a bandgap voltage of about 1.2 volts.

5. The integrated circuit of claim 4 , wherein the reference voltage circuit includes a fraction control circuit coupled to the first capacitor, and
wherein the fraction control circuit is configured to determine a ratio of the reference voltage to the bandgap voltage.

6. The integrated circuit of claim 5 , wherein the fraction control circuit includes:
one or more fraction control capacitors, each fraction control capacitor coupled to a fraction control switch;
wherein the fraction control circuit is configured to receive a fraction control signal, and
wherein each fraction control switch is controlled by a bit of the fraction control signal.

7. The integrated circuit of claim 6 , wherein the reference voltage is first order temperature independent.

8. The integrated circuit of claim 7 , wherein the integrated circuit includes an analog-to-digital converter (ADC) having a first input, a second input, and a first output;
wherein the first input of the ADC is configured to receive an analog voltage signal,
wherein the second input of the ADC is configured to receive the reference voltage, and
wherein the first output of the ADC provides a digital signal corresponding to the analog voltage signal.

9. The integrated circuit of claim 8 , wherein the ADC includes a second output providing the fraction control signal to the fraction control circuit.

10. A method, comprising:
receiving, by a bipolar junction transistor (BJT), a first current during a first phase of a clock cycle to generate a first base-emitter junction voltage;
receiving, by the BJT, a second current during a second phase of the clock cycle to generate a second base-emitter junction voltage; and
providing, by a switched capacitor circuit, a reference voltage associated with the first base-emitter junction voltage and the second base-emitter junction voltage, wherein the providing the reference voltage associated with the first base-emitter junction voltage and the second base-emitter junction voltage includes:
storing, by a first capacitor of the switched capacitor circuit, a first charge associated with the first base-emitter junction voltage during the first phase;
storing, by a second capacitor of the switch capacitor circuit, a second charge associated with a difference between the first and second base-emitter junction voltage during the second phase; and redistributing, the between the first and second capacitors, the first charge and second charge during a third phase of the clock cycle.

11. The method of claim 10 , further comprising:
receiving a supply voltage less than about 1.5 volts.

12. The method of claim 10 , further comprising:
coupling the first capacitor to a first input of an operational amplifier;
coupling the second capacitor to a second input of the operational amplifier; and
providing the reference voltage using an output of the operational amplifier.

13. The method of claim 10 , wherein the reference voltage is equal to or less than a bandgap voltage of about 1.2 volts.

14. The method of claim 13 , further comprising:
determining a ratio of the reference voltage to the bandgap voltage using a fraction control circuit coupled to the first capacitor.

15. The method of claim 14 , further comprising:
receiving, by the fraction control circuit, a fraction control signal;
wherein the fraction control circuit includes one or more fraction control capacitors, each fraction control capacitor coupled to a fraction control switch; and
wherein each fraction control switch is controlled by a bit of the fraction control signal.

16. The method of claim 15 , wherein the reference voltage is first order temperature independent.

17. The method of claim 16 , further comprising:
providing an analog signal to a first input of an analog-to-digital converter (ADC);
providing the reference voltage to a second input of the ADC; and
generating, through a first output of the ADC, a digital signal corresponding to the analog signal.

18. The method of claim 17 , further comprising:
receiving, by the fraction control circuit from the ADC, the fraction control signal.

Assignees

• Xilinx Inc

Inventors

• Kamath Umanath R
• Jennings John K

Classifications

• G05F1/468 Primary

  characterised by reference voltage circuitry, e.g. soft start, remote shutdown · CPC title

• G05F3/30

  Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities (G05F3/26 takes precedence) · CPC title