Dynamic element matching in an integrated circuit

Patent metadata

Field	Value
Publication number	US-2018356294-A1
Application number	US-201715616765-A
Country	US
Kind code	A1
Filing date	Jun 7, 2017
Priority date	Jun 7, 2017
Publication date	Dec 13, 2018
Grant date	—

Abstract

An example dynamic element matching (DEM) circuit includes: a plurality of bipolar junction transistors (BJTs), each of the plurality of BJTs having a base terminal and a collector terminal coupled to electrical ground; a plurality of pairs of force switches, each pair of force switches coupled to an emitter of a respective one of the plurality of BJTs; a plurality of pairs of sense switches, where each pair of sense switches is coupled to the emitter of a respective one of the plurality of BJTs, a first switch in each pair of sense switches is coupled to a first node, and a second switch in each pair of sense switches is coupled to a second node; a first current source coupled to a first switch in each pair of force switches; and a second current source coupled to a second switch in each pair of force switches.

First claim

1 . A dynamic element matching (DEM) circuit, comprising:
a plurality of bipolar junction transistors (BJTs), each of the plurality of BJTs having a base terminal and a collector terminal coupled to electrical ground; a plurality of pairs of force switches, each pair of force switches coupled to an emitter of a respective one of the plurality of BJTs; a plurality of pairs of sense switches, where each pair of sense switches is coupled to the emitter of a respective one of the plurality of BJTs, a first switch in each pair of sense switches is coupled to a first node, and a second switch in each pair of sense switches is coupled to a second node; a first current source coupled to a first switch in each pair of force switches; and a second current source coupled to a second switch in each pair of force switches.

2 . The DEM circuit of claim 1 , further comprising:
a switch controller coupled to the plurality of pairs of force switches and the plurality of pairs of sense switches.

3 . The DEM circuit of claim 2 , wherein the switch controller is configured to generate a plurality of differential logic signal pairs, where each pair of sense switches and each pair of force switches receives a respective one of the plurality of differential logic signal pairs.

4 . The DEM circuit of claim 3 , wherein the first switch in each pair of the force switches receives a true logic signal of a respective differential logic signal pair and the second switch in each pair of the force switches receives a complement logic signal of the respective differential logic signal pair.

5 . The DEM circuit of claim 4 , wherein the first switch in each pair of the sense switches receives the true logic signal of the respective differential logic signal pair and the second switch in each pair of the sense switches receives the complement logic signal of the respective differential logic signal pair.

6 . The DEM circuit of claim 1 , wherein a first current supplied by the first current source and a second current supplied by the second current source is substantially the same.

7 . The DEM circuit of claim 1 , wherein a first current supplied by the first current source is greater than a second current supplied by the second current source or the second current is greater than the first current.

8 . An integrated circuit (IC), comprising:
a system monitor circuit; and at least one dynamic element matching (DEM) circuit coupled to the system monitor circuit, each of the at least one DEM circuit comprising:
a plurality of bipolar junction transistors (BJTs), each of the plurality of BJTs having a base terminal and a collector terminal coupled to electrical ground;
a plurality of pairs of force switches, each pair of force switches coupled to an emitter of a respective one of the plurality of BJTs;
a plurality of pairs of sense switches, where each pair of sense switches is coupled to the emitter of a respective one of the plurality of BJTs, a first switch in each pair of sense switches is coupled to a first node, and a second switch in each pair of sense switches is coupled to a second node;
a first current source coupled to a first switch in each pair of force switches; and
a second current source coupled to a second switch in each pair of force switches.

9 . The IC of claim 8 , further comprising:
a switch controller coupled to the plurality of pairs of force switches and the plurality of pairs of sense switches.

10 . The IC of claim 9 , wherein the switch controller is configured to generate a plurality of differential logic signal pairs, where each pair of sense switches and each pair of force switches receives a respective one of the plurality of differential logic signal pairs.

11 . The IC of claim 10 , wherein the first switch in each pair of the force switches receives a true logic signal of a respective differential logic signal pair and the second switch in each pair of the force switches receives a complement logic signal of the respective differential logic signal pair.

12 . The IC of claim 11 , wherein the first switch in each pair of the sense switches receives the true logic signal of the respective differential logic signal pair and the second switch in each pair of the sense switches receives the complement logic signal of the respective differential logic signal pair.

13 . The IC of claim 8 , wherein a first current supplied by the first current source and a second current supplied by the second current source is substantially the same.

14 . The IC of claim 8 , wherein each of the at least one DEM circuit is a temperature sensing circuit.

15 . A method of dynamic element matching (DEM) in an integrated circuit (IC), comprising:
controlling force switches and sense switches coupled to emitters in an array of diode-connected bipolar junction transistors (BJTs) over a plurality of cycles, each cycle including: injecting a first current into a selected one of the diode-connected BJTs; injecting a second current into a circuit formed by remaining ones of the diode-connected BJTs; coupling the emitter of the selected one of the diode-connected BJTs to a first node; and coupling the emitter of the remaining ones of the diode-connected BJTs to a second node.

16 . The method of claim 15 , wherein the step of controlling comprises, for each cycle, measuring voltage of the first node with respect to the second node.

17 . The method of claim 15 , wherein the step of controlling comprises performing the plurality of cycles in each of a plurality of sensing periods.

18 . The method of claim 15 , wherein the BJTs are coupled between the force switches and electrical ground, and wherein the sense switches are coupled between the emitters and the first and second nodes.

19 . The method of claim 18 , wherein the force switches include a pair of switches coupled to each of the emitters, and wherein the sense switches include a pair of switches coupled to each of the emitters.

20 . The method of claim 15 , wherein a first current and a second current are substantially the same.

Assignees

• Xilinx Inc

Inventors

• Kamath Umanath R
• Kelly Padraig
• Jennings John K

Classifications

• G01K1/026 Primary

  arrangements for monitoring a plurality of temperatures, e.g. by multiplexing · CPC title

• G01K7/015

  using microstructures, e.g. made of silicon · CPC title

• H03K19/017581

  programmable · CPC title

• H03K19/00307 Primary

  in bipolar transistor circuits · CPC title

• G01K7/01 Primary

  using semiconducting elements having PN junctions (G01K7/02, G01K7/16, G01K7/30 take precedence) · CPC title