Trim techniques for voltage reference circuits

Patent metadata

Field	Value
Publication number	US-10120399-B1
Application number	US-201715848357-A
Country	US
Kind code	B1
Filing date	Dec 20, 2017
Priority date	Dec 20, 2017
Publication date	Nov 6, 2018
Grant date	Nov 6, 2018

Abstract

An example method of trimming a voltage reference in an integrated circuit (IC) includes at a first temperature, sequencing through a first plurality of trim codes for a reference circuit of the voltage reference configured to generate a proportional-to-temperature current and a corresponding first control voltage, and a complementary-to-temperature current and a corresponding second control voltage. The method further includes measuring a voltage output of the voltage reference for each of the first plurality of trim codes to obtain first voltage output values. The method further includes at a second temperature, sequencing through a second plurality of trim codes for the reference circuit. The method further includes measuring the voltage output of the voltage reference for each of the second plurality of trim codes to obtain second voltage output values. The method further includes selecting a trim code for the reference circuit based on the first voltage output values and the second voltage output values.

First claim

What is claimed is:

1. A method of trimming a voltage reference in an integrated circuit (IC), comprising:
at a first temperature, sequencing through a first plurality of trim codes for a reference circuit of the voltage reference configured to generate a proportional-to-temperature current and a corresponding first control voltage, and a complementary-to-temperature current and a corresponding second control voltage;
measuring a voltage output of the voltage reference for each of the first plurality of trim codes to obtain first voltage output values;
at a second temperature, sequencing through a second plurality of trim codes for the reference circuit;
measuring the voltage output of the voltage reference for each of the second plurality of trim codes to obtain second voltage output values; and
selecting a trim code for the reference circuit based on the first voltage output values and the second voltage output values.

2. The method of claim 1 , further comprising:
fitting the first voltage output values to a polynomial; and
storing one or more first coefficients of the polynomial in the IC.

3. The method of claim 2 , further comprising:
fitting the second voltage output values to the polynomial to generate one or more second coefficients; and
determining an intersection between a first curve generated using the one or more first coefficients and a second curve generated using the one or more second coefficients.

4. The method of claim 3 , wherein the step of selecting the trim code comprises determining the trim code from the intersection between the first curve and the second curve.

5. The method of claim 1 , further comprising:
adjusting trim of a temperature coefficient (Tempco) circuit, controlled by the reference circuit to generate the voltage output, to set the voltage output to a desired voltage.

6. The method of claim 1 , wherein the reference circuit comprises:
a first field effect transistor (FET) and a second FET having a first common source and a first common gate;
a first diode-connected bipolar junction transistor (BJT) coupled between a drain of the first FET and a ground node;
a first resistor and a second diode-connected BJT coupled in series between a drain of the second FET and the ground node;
a first operational amplifier having a non-inverting input coupled to the drain of the second FET, an inverting input coupled to the drain of the first FET, and an output coupled to the first common gate;
a third FET having a source coupled to the common source;
a resistor ladder coupled between a drain of the third FET and the ground node; and
a second operational amplifier having an inverting input coupled to the drain of the first FET, a non-inverting input coupled to the resistor ladder, and an output coupled to a gate of the third FET.

7. The method of claim 1 , wherein the voltage reference includes:
a first current source coupled to a first load circuit, the first current source generating a sum current of the proportional-to-temperature current and the complementary-to-temperature current in response to the first and second control voltages, the first load circuit generating a zero temperature coefficient (Tempco) voltage from the sum current; and
a second current source coupled to a second load circuit, the second current source generating the sum current of the proportional-to-temperature current and the complementary-to-temperature current in response to the first and second control voltages, the second load circuit generating a negative Tempco voltage from the sum current and the complementary-to-temperature current.

8. The method of claim 7 , wherein the first current source comprises a first field effect transistor (FET) and a second FET having a first common source and a first common drain, a gate of the first FET coupled to receive the first control voltage and a gate of the second FET coupled to receive the second control voltage, and wherein the first load circuit comprises a resistor ladder coupled between the first common drain and a ground node, the resistor ladder converting the sum current into the zero Tempco voltage.

9. The method of claim 7 , wherein the second current source comprises:
a first field effect transistor (FET) and a second FET having a first common source and a first common drain, a gate of the first FET coupled to receive the first control voltage and a gate of the second FET coupled to receive the second control voltage; and
a third FET having a gate coupled to the second control voltage; and
wherein the second load circuit comprises:
a first resistor ladder and a second resistor ladder coupled in series between the first common drain and a ground node, the first and second resistor ladders receiving the sum current from the first common drain, a portion of the second resistor ladder receiving the complementary-to-temperature current from a drain of the third FET.

10. The method of claim 7 , wherein the voltage reference includes:
a third current source coupled to a third load circuit, the third current source generating the sum current of the proportional-to-temperature current and the complementary-to-temperature current in response to the first and second control voltages, the third load circuit generating a positive Tempco voltage from the sum current and at least one of the complementary-to-temperature current and the proportional-to-temperature current.

11. An apparatus for trimming a voltage reference in an integrated circuit (IC), comprising:
a memory; and
a processor configured to execute code stored in the memory to:
at a first temperature, sequence through a first plurality of trim codes for a reference circuit of the voltage reference configured to generate a proportional-to-temperature current and a corresponding first control voltage, and a complementary-to-temperature current and a corresponding second control voltage;
measure a voltage output of the voltage reference for each of the first plurality of trim codes to obtain first voltage output values;
at a second temperature, sequence through a second plurality of trim codes for the reference circuit;
measure the voltage output of the voltage reference for each of the second plurality of trim codes to obtain second voltage output values; and
select a trim code for the reference circuit based on the first voltage output values and the second voltage output values.

12. The apparatus of claim 11 , wherein the processor is further configured to execute the code to:
fit the first voltage output values to a polynomial; and
store one or more first coefficients of the polynomial in the IC.

13. The apparatus of claim 12 , wherein the processor is further configured to execute the code to:
fit the second voltage output values to the polynomial to generate one or more second coefficients; and
determine an intersection between a first curve generated using the one or more first coefficients and a second curve generated using the one or more second coefficients.

14. The apparatus of claim 13 , wherein the processor selects the trim code by determining the trim code from the intersection between the first curve and the second curve.

15. The apparatus of claim 11 , wherein the processor is further configured to execute the code to:
adjust trim of a temperature coefficient (Tempco) circuit, controlled by the reference circuit to generate the voltage output, to set the voltage output to a desired voltage.

16. The apparatus of claim 11 , wherein the reference circuit comprises:
a first field effect transistor (FET) and a second FET having a

Assignees

• Xilinx Inc

Inventors

• Kamath Umanath R
• Cullen Edward
• Jennings John K

Classifications

• G05F1/461

  using an operational amplifier as final control device · CPC title

• G06F1/206

  comprising thermal management · CPC title

• G05F1/468 Primary

  characterised by reference voltage circuitry, e.g. soft start, remote shutdown · CPC title

• G06F1/26

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title