Analog switch having reduced gate-induced drain leakage

Patent metadata

Field	Value
Publication number	US-2016277019-A1
Application number	US-201514659747-A
Country	US
Kind code	A1
Filing date	Mar 17, 2015
Priority date	Mar 17, 2015
Publication date	Sep 22, 2016
Grant date	—

Abstract

In an example, an apparatus includes an analog switch having an n-type metal oxide semiconductor (NMOS) circuit in parallel with a p-type metal oxide semiconductor (PMOS) circuit between a switch input and a switch output. The analog switch is responsive to an enable signal that determines switch state thereof. The NMOS circuit includes a switch N-channel transistor coupled to a buffer N-channel transistor, a gate of the switch N-channel transistor coupled to the enable signal and a gate of the buffer N-channel transistor coupled to a modulated N-channel gate voltage. The PMOS circuit including a switch P-channel transistor coupled to a buffer P-channel transistor, a gate of the switch P-channel transistor coupled to a complement of the enable signal and a gate of the buffer P-channel transistor coupled to a modulated P-channel gate voltage. A control circuit is coupled to the analog switch to provide the modulated N-channel and modulated P-channel gate voltages each of which alternates between a respective supply voltage and a respective gate induced drain leakage (GIDL) mitigation voltage based on the switch state.

First claim

What is claimed is:

1 . An apparatus, comprising:
an analog switch including an n-type metal oxide semiconductor (NMOS) circuit in parallel with a p-type metal oxide semiconductor (PMOS) circuit between a switch input and a switch output, the analog switch responsive to an enable signal that determines switch state thereof; the NMOS circuit including a switch N-channel transistor coupled to a buffer N-channel transistor, a gate of the switch N-channel transistor coupled to the enable signal and a gate of the buffer N-channel transistor coupled to a modulated N-channel gate voltage; the PMOS circuit including a switch P-channel transistor coupled to a buffer P-channel transistor, a gate of the switch P-channel transistor coupled to a complement of the enable signal and a gate of the buffer P-channel transistor coupled to a modulated P-channel gate voltage; and a control circuit coupled to the analog switch to provide the modulated N-channel and modulated P-channel gate voltages each of which alternates between a respective supply voltage and a respective gate induced drain leakage (GIDL) mitigation voltage based on the switch state.

2 . The apparatus of claim 1 , wherein each of the modulated N-channel and modulated P-channel gate voltages is a respective supply voltage when the switch state is on and a respective GIDL mitigation voltage when the switch state is off.

3 . The apparatus of claim 2 , wherein:
the modulated N-channel gate voltage alternates between a respective supply voltage being a first supply voltage and a respective GIDL mitigation voltage being a first GIDL mitigation voltage; and the modulated P-channel gate voltage alternates between a respective supply voltage being a second supply voltage and a respective GIDL mitigation voltage being a second GIDL mitigation voltage.

4 . The apparatus of claim 3 , wherein the first supply voltage comprises a positive voltage and the second supply voltage comprises a reference voltage, and wherein the first and second GIDL mitigation voltages are between the positive voltage and the reference voltage.

5 . The apparatus of claim 4 , wherein each of the first and second GIDL mitigation voltages are approximately equal to half of the difference between the positive voltage and the reference voltage.

6 . The apparatus of claim 1 , wherein the control circuit comprises:
a first circuit coupled to apply the modulated N-channel gate voltage to the gate of the buffer N-channel transistor; and a second circuit coupled to apply the modulated P-channel gate voltage to the gate of the buffer P-channel transistor.

7 . The apparatus of claim 6 , wherein the first circuit comprises:
an N-channel transistor having a source coupled to the first GIDL mitigation voltage, a drain coupled to the gate of the buffer N-channel transistor, and a gate coupled to the complement of the enable signal; and a P-channel transistor having a source coupled to the first supply voltage, a drain coupled to the gate of the buffer N-channel transistor, and a gate coupled to the complement of the enable signal.

8 . The apparatus of claim 6 , wherein the second circuit comprises:
a first N-channel transistor having a source coupled to the second GIDL mitigation voltage, a drain coupled to the gate of the buffer P-channel transistor, and a gate coupled to the complement of the enable signal; and a second N-channel transistor having a source coupled to the second supply voltage, a drain coupled to the gate of the buffer P-channel transistor, and a gate coupled to the enable signal.

9 . The apparatus of claim 1 , wherein the buffer N-channel transistor and the buffer P-channel transistor are coupled between the switch output and respective drains of the switch N-channel transistor and the switch P-channel transistor.

10 . The apparatus of claim 1 , wherein the buffer N-channel transistor and the buffer P-channel transistor are coupled between the switch input and respective sources of the switch N-channel transistor and the switch P-channel transistor.

11 . The apparatus of claim 10 , wherein:
the buffer N-channel transistor comprises an input buffer N-channel transistor and the buffer P-channel transistor comprises an input buffer P-channel transistor; the NMOS circuit includes an output buffer N-channel transistor coupled between the switch output and a drain of the switch N-channel transistor, a gate of the output buffer N-channel transistor coupled to the modulated N-channel gate voltage; and the PMOS circuit includes an output buffer P-channel transistor coupled between the switch output and a drain of the switch P-channel transistor, a gate of the output buffer P-channel transistor coupled to the modulated P-channel gate voltage.

12 . An apparatus, comprising:
a plurality of analog switches coupled to a common terminal, each of the plurality of analog switches responsive to a respective enable signal that determines switch state thereof, each of the plurality of analog switches comprising:
an n-type metal oxide semiconductor (NMOS) circuit in parallel with a p-type metal oxide semiconductor (PMOS) circuit between a switch input and a switch output;
the NMOS circuit including a switch N-channel transistor coupled to a buffer N-channel transistor, a gate of the switch N-channel transistor coupled to the respective enable signal and a gate of the buffer N-channel transistor coupled to a modulated N-channel gate voltage;
the PMOS circuit including a switch P-channel transistor coupled to a buffer P-channel transistor, a gate of the switch P-channel transistor coupled to a complement of the respective enable signal and a gate of the buffer P-channel transistor coupled to a modulated P-channel gate voltage; and
a control circuit coupled to NMOS and PMOS circuits to provide the modulated N-channel and modulated P-channel gate voltages each of which alternates between a respective supply voltage and a respective gate induced drain leakage (GIDL) mitigation voltage based on the switch state.

13 . The apparatus of claim 12 , wherein each of the modulated N-channel and modulated P-channel gate voltages is a respective supply voltage when the switch state is on and a respective GIDL mitigation voltage when the switch state is off.

14 . The apparatus of claim 13 , wherein:
the modulated N-channel gate voltage alternates between a respective supply voltage being a first supply voltage and a respective GIDL mitigation voltage being a first GIDL mitigation voltage; and the modulated P-channel gate voltage alternates between a respective supply voltage being a second supply voltage and a respective GIDL mitigation voltage being a second GIDL mitigation voltage.

15 . The apparatus of claim 14 , wherein the first supply voltage comprises a positive voltage and the second supply voltage comprises a reference voltage, and wherein the first and second GIDL mitigation voltages are between the positive voltage and the reference voltage.

16 . The apparatus of claim 12 , wherein the control circuit comprises:
a first circuit coupled to apply the modulated N-channel gate voltage to the gate of the buffer N-channel transistor, the first circuit including:
an N-channel transistor having a source coupled to the first GIDL mitigation voltage, a drain coupled to the gate of the buffer N-channel transistor, and a gate coupled to the complement of the enable signal; and
a P-channel transistor having a source coupled to the first supply voltage, a drain coupled to the gate of the buffer N-channel transistor, and a gate coupled to the complement of the enab

Assignees

• Xilinx Inc

Inventors

• Cical Ionut C
• Jennings John K
• Durbha Chandrika

Classifications

• H03K17/165

  by feedback from the output circuit to the control circuit · CPC title

• H03K3/012

  Modifications of generator to improve response time or to decrease power consumption · CPC title

• H03K17/063 Primary

  in field-effect transistor switches · CPC title

• H03K2217/0054

  Gating switches, e.g. pass gates · CPC title

• H03K17/161 Primary

  in field-effect transistor switches · CPC title