Stacked memory with interface providing offset interconnects
US-2024379625-A1 · Nov 14, 2024 · US
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Halbert John B patents
Halbert John B is listed as an inventor on 86 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Halbert John B |
| Total patents | 86 |
| First publication | Jan 20, 2015 |
| Latest publication | Nov 14, 2024 |
Notable patents
Publications ranked by popularity score, then publication date.
Stacked memory with interface providing offset interconnects
US-12046577-B2 · Jul 23, 2024 · US
Memory with reduced exposure to manufacturing related data corruption errors
US-11010304-B2 · May 18, 2021 · US
On-die ECC with error counter and internal address generation
US-10949296-B2 · Mar 16, 2021 · US
Memory device error check and scrub mode and error transparency
US-10810079-B2 · Oct 20, 2020 · US
Targeted aliasing single error correction (SEC) code
US-10572343-B2 · Feb 25, 2020 · US
Performance of additional refresh operations during self-refresh mode
US-10522207-B2 · Dec 31, 2019 · US
Extracting selective information from on-die dynamic random access memory (DRAM) error correction code (ECC)
US-10496473-B2 · Dec 3, 2019 · US
Flexible command addressing for memory
US-10489083-B2 · Nov 26, 2019 · US
Stacked memory chip device with enhanced data protection capability
US-10459809-B2 · Oct 29, 2019 · US
Recent patents
Latest publications not already listed above.
Stacked memory with interface providing offset interconnects
US-2019304953-A1 · Oct 3, 2019 · US
Memory chip having reduced baseline refresh rate with additional refreshing for weak cells
US-2019096472-A1 · Mar 28, 2019 · US
Reduction of power consumption in memory devices during refresh modes
US-10242727-B2 · Mar 26, 2019 · US
Memory device error check and scrub mode and error transparency
US-2019073261-A1 · Mar 7, 2019 · US
Row hammer refresh command
US-10210925-B2 · Feb 19, 2019 · US
Memory with reduced exposure to manufacturing related data corruption errors
US-2019042449-A1 · Feb 7, 2019 · US
Stacked memory chip device with enhanced data protection capability
US-2019004909-A1 · Jan 3, 2019 · US
Reduction of power consumption in memory devices during refresh modes
US-2018336943-A1 · Nov 22, 2018 · US
Memory device error check and scrub mode and error transparency
US-10127101-B2 · Nov 13, 2018 · US
Apparatus, method and system for performing successive writes to a bank of a dynamic random access memory
US-10121532-B2 · Nov 6, 2018 · US
Validation of memory on-die error correction code
US-10108512-B2 · Oct 23, 2018 · US
Precharging and refreshing banks in memory device with bank group architecture
US-10109340-B2 · Oct 23, 2018 · US
Row hammer monitoring based on stored row hammer threshold value
US-10083737-B2 · Sep 25, 2018 · US
Targeted aliasing single error correction (sec) code
US-2018203761-A1 · Jul 19, 2018 · US
Row hammer refresh command
US-2018174639-A1 · Jun 21, 2018 · US
Reduction of power consumption in memory devices during refresh modes
US-9984737-B2 · May 29, 2018 · US
Increased redundancy in multi-device memory package to improve reliability
US-2018137005-A1 · May 17, 2018 · US
STACKED MEMORY WITH INTERFACE PROVIDING OFFSET Interconnect S
US-2018122779-A1 · May 3, 2018 · US
Memory controller-controlled refresh abort
US-9953694-B2 · Apr 24, 2018 · US
Staggering initiation of refresh in a group of memory devices
US-2018096719-A1 · Apr 5, 2018 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Intel Corp | 83 |
| Halbert John B | 10 |
| Bains Kuljit S | 9 |
| Schoenborn Theodore Z | 2 |
| Mozak Christopher P | 2 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G11C11/40611 | 36 |
| G11C29/52 | 22 |
| G11C11/40618 | 22 |
| G11C11/406 | 21 |
| G11C11/4076 | 21 |