Row hammer refresh command

Patent metadata

Field	Value
Publication number	US-10210925-B2
Application number	US-201715835050-A
Country	US
Kind code	B2
Filing date	Dec 7, 2017
Priority date	Jun 30, 2012
Publication date	Feb 19, 2019
Grant date	Feb 19, 2019

Abstract

A memory controller issues a targeted refresh command. A specific row of a memory device can be the target of repeated accesses. When the row is accessed repeatedly within a time threshold (also referred to as “hammered” or a “row hammer event”), physically adjacent row (a “victim” row) may experience data corruption. The memory controller receives an indication of a row hammer event, identifies the row associated with the row hammer event, and sends one or more commands to the memory device to cause the memory device to perform a targeted refresh that will refresh the victim row.

First claim

What is claimed is:

1. A memory controller comprising:
an interface circuit to couple to a memory device having multiple rows of memory; and
control logic to generate a mode register command to set one or more bits of a mode register of the memory device to trigger the memory device to enter a targeted refresh mode in response to a number of activates of a target row of the multiple rows within a time period to meet or exceed a threshold, and while the memory device is in the targeted refresh mode, the control logic to send via the interface circuit one or more commands to cause refresh of only a limited number of rows physically proximate to the target row including refresh of a victim row.

2. The memory controller of claim 1 , wherein the time period comprises a refresh window.

3. The memory controller of claim 1 , wherein while the memory device is in the target refresh mode, the control logic is to send an activate command followed by a precharge command.

4. The memory controller of claim 1 , wherein the control logic is to send the one or more commands including a target row address with target bank group and target bank address.

5. The memory controller of claim 4 , wherein the memory device is to identify an address of the victim row.

6. The memory controller of claim 1 , wherein the victim row comprises a row physically adjacent to the target row.

7. The memory controller of claim 1 , wherein the memory device includes a dynamic random access memory (DRAM) device compliant with a double data rate version 4 (DDR4) standard or compliant with a wide input/output (WIO) memory standard.

8. The memory controller of claim 1 , further comprising a detector in the memory controller to determine that the number of activates of the target row within the time period meets or exceeds the threshold.

9. A system comprising:
a memory device including
a mode register to store one or more bits to control entry of the memory device into a targeted refresh mode; and
multiple rows of memory;

a memory controller including
an interface circuit to couple to the memory device; and
control logic to generate a mode register command to set one or more bits of a mode register of the memory device to trigger the memory device to enter a targeted refresh mode in response to a number of activates of a target row of the multiple rows within a time period to meet or exceed a threshold, and while the memory device is in the targeted refresh mode, the control logic to send via the interface circuit one or more commands to cause refresh of only a limited number of rows physically proximate to the target row including refresh of a victim row; and

a detector logic to determine that the number of activates of the target row within the time period meets or exceeds the threshold.

10. The system of claim 9 , wherein the time period comprises a refresh window.

11. The system of claim 9 , wherein while the memory device is in the target refresh mode, the control logic is to send an activate command followed by a precharge command.

12. The system of claim 9 , wherein the control logic is to send the one or more commands including a target row address with target bank group and target bank address.

13. The system of claim 12 , wherein the memory device is to identify an address of the victim row.

14. The system of claim 9 , wherein the victim row comprises a row physically adjacent to the target row.

15. The system of claim 9 , wherein the memory device includes a dynamic random access memory (DRAM) device compliant with a double data rate version 4 (DDR4) standard or compliant with a wide input/output (WIO) memory standard.

16. The system of claim 9 , further comprising a detector in the memory controller to determine that the number of activates of the target row within the time period meets or exceeds the threshold.

17. The system of claim 9 , further comprising one or more of:
at least one processor communicatively coupled to the memory controller;
a display communicatively coupled to display data from the memory device;
a battery to power the system; or
a network interface communicatively coupled to exchange data stored in the memory device with a remote device over a network connection.

18. A method for memory refresh comprising:
sending a mode register set command to set a memory device in a targeted refresh mode in response to a number of activates of a target row within a time period meets or exceeds a threshold; and
sending one or more commands in the targeted refresh mode to cause the memory device to refresh only a limited number of rows physically proximate to the target row including refresh of a victim row in response to the one or more commands in the targeted refresh mode.

19. The method of claim 18 , wherein sending the one or more commands in the targeted refresh mode comprises sending an activate command followed by a precharge command, including sending a target row address.

20. The method of claim 18 , wherein refresh of the victim row comprises refresh of one or more rows physically adjacent to the target row.

Assignees

• Intel Corp

Inventors

• Bains Kuljit S
• Halbert John B
• Mozak Christopher P
• Schoenborn Theodore Z
• Greenfield Zvika

Classifications

• G11C11/40622

  Partial refresh of memory arrays · CPC title

• G06F2212/7211

  Wear leveling · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G11C11/406 Primary

  Management or control of the refreshing or charge-regeneration cycles · CPC title

• G11C11/40611 Primary

  External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh · CPC title