Reduction of power consumption in memory devices during refresh modes

Patent metadata

Field	Value
Publication number	US-9984737-B2
Application number	US-201615354200-A
Country	US
Kind code	B2
Filing date	Nov 17, 2016
Priority date	Mar 27, 2012
Publication date	May 29, 2018
Grant date	May 29, 2018

Abstract

Devices, systems, and methods include an active mode to accommodate read/write operations of a memory device and a self-refresh mode to accommodate recharging of voltage levels representing stored data when read/write operations are idle. At least one register source provides a first voltage level and a second voltage level that is less than the first voltage level. With such a configuration, during the active mode, the memory device operates at the first voltage level as provided by the at least one register source, and during the self-refresh mode, the memory device operates at the second voltage level as provided by the at least one register source.

First claim

What is claimed is:

1. A memory device comprising:
a memory array; and
circuitry to:
operate from a first voltage rail in a first mode, wherein the first voltage rail is to provide a first DC voltage at a first magnitude, and wherein the first mode is to accommodate read and write operations to access the memory array,
operate from a second voltage rail in a second mode based at least in part on a register, wherein the second voltage rail is to provide a second DC voltage at a second magnitude that is lower than the first magnitude, and wherein the memory device is to perform self-refresh in the second mode.

2. The memory device of claim 1 , further comprising:
the register to store a value to indicate whether the memory device is to operate from the first or second voltage rail.

3. The memory device of claim 1 , wherein the register comprises a mode register or a multipurpose register.

4. The memory device of claim 1 , wherein a voltage regulator is to supply voltage to the first and second voltage rails to the memory device.

5. The memory device of claim 1 , wherein:
the circuitry is to be switched from the first voltage rail to the second voltage rail based in part on a transition to the second mode.

6. The memory device of claim 1 , wherein:
the circuitry is to be switched from the first voltage rail to the second voltage rail based in part on the register.

7. The memory device of claim 1 , wherein:
the circuitry is to be switched from the first voltage rail to the second voltage rail based at least in part on a second register, wherein the second register is to indicate whether operation from the second voltage rail is enabled.

8. A method comprising:
operating circuitry of a memory device from a first voltage rail in a first mode, wherein the first voltage rail is to provide a first DC voltage at a first magnitude, and wherein the first mode accommodates read and write operations;
transitioning to a second mode, wherein the memory device is to perform self-refresh operations in the second mode; and
operating the circuitry of the memory device from a second voltage rail in the second mode based at least in part on a register, wherein the second voltage rail is to provide a second DC voltage at a second magnitude that is lower than the first magnitude.

9. The method of claim 8 , comprising:
causing a switch from the first voltage rail to the second voltage rail is based at least in part on a transition to the second mode.

10. The method of claim 8 , wherein:
causing a switch from the first voltage rail to the second voltage rail is based at least in part on the register.

11. The method of claim 8 , wherein:
causing a switch from the first voltage rail to the second voltage rail is based at least in part on a second register, wherein the second register is to indicate whether operation from the second voltage rail is enabled.

12. The method of claim 8 , further comprising:
storing a value in the register to indicate whether the memory device is to operate from the first or second voltage rail.

13. The method of claim 12 , wherein the register comprises a mode register or a multipurpose register.

Assignees

• Intel Corp

Inventors

• Cox Christopher E
• Bains Kuljit Singh
• Halbert John B

Classifications

• G11C11/4074 Primary

  Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits · CPC title

• G11C11/4096

  Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches · CPC title

• G11C7/00

  Arrangements for writing information into, or reading information out from, a digital store (G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413) · CPC title

• G11C7/08

  Control thereof · CPC title

• G11C11/40615 Primary

  Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs · CPC title