Apparatus, method and system for performing successive writes to a bank of a dynamic random access memory

Patent metadata

Field	Value
Publication number	US-10121532-B2
Application number	US-201715640250-A
Country	US
Kind code	B2
Filing date	Jun 30, 2017
Priority date	Dec 8, 2014
Publication date	Nov 6, 2018
Grant date	Nov 6, 2018

Abstract

Techniques and mechanisms to provide write access to a memory device. In an embodiment, a memory controller sends commands to a memory device which comprises multiple memory banks. The memory controller further sends a signal specifying that the commands include back-to-back write commands each to access the same memory bank. In response to the signal, the memory device buffers first data of a first write command, wherein the first data is buffered at least until the memory device receives second data of a second write command. Error correction information is calculated for a combination of the first data and second data, and the combination is written to the memory bank. In another embodiment, buffering of the first data and combining of the first data with the second data is performed, based on the signal from the memory controller, in lieu of read-modify-write processing of the first data.

First claim

What is claimed is:

1. An apparatus comprising:
input/output (I/O) circuitry to receive signals;
a plurality of memory arrays arranged in memory banks;
detector logic including circuitry to detect a signal that indicates two or more received commands include successive write commands to a same memory bank of the plurality of memory arrays, the signal encoded in a write command address strobe (write CAS) command;
a buffer to store first write data of the successive write commands until a receipt of second write data of the successive write commands responsive to an indication from the detector logic that the signal was detected; and
error correction logic to calculate error check information based on the first write data and the second write data.

2. The apparatus of claim 1 , comprising the signal encoded in the write CAS command via setting an address bit from among a plurality of address bits for the write CAS command to indicate that two or more received commands include successive write commands.

3. The apparatus of claim 2 , comprising the detector logic to detect the signal based on a determination that the address bit from among the plurality of address bits is set to a value of 1.

4. The apparatus of claim 1 , comprising if the detector logic detects the signal encoded in the write CAS command, the detector logic to cause the buffer to store the second write data, concurrently with the first write data, until a receipt of third write data of the successive write commands.

5. The apparatus of claim 1 , further comprising
access logic including circuitry to facilitate access to the memory banks of the plurality of memory arrays;
if the detector logic fails to detect the signal encoded in the write CAS command, the detector logic to indicate to the access logic to perform a first read-modify-write operation to cause the first write data to be stored to at least one of the memory banks of the plurality of memory arrays.

6. The apparatus of claim 1 , further comprising:
prefetch logic including circuitry to perform a prefetch of bits of data from one or more memory banks of the plurality of memory arrays, a first total number of the bits of data for the prefetch is greater than a second total number of bits of data included in the first write data or a third total number of bits of data included in the second write data.

7. The apparatus of claim 1 , comprising:
access logic including circuitry to facilitate access to the memory banks of the plurality of memory arrays;
the error correction logic to calculate error check information includes the error correction logic to calculate an error check value based on a combination of the first write data and the second write data, the access logic to write the error check information and the combination of the first write data and the second write data to the same memory bank of the memory banks of the plurality of memory arrays.

8. The apparatus of claim 1 , the plurality of memory arrays includes dynamic random access memory (DRAM), NAND flash memory, phase change memory, resistive memory, nanowire memory, ferrorelectric transistor random access memory (FeTRAM), magnetoresistive random access memory (MRAM) or spin transfer torque MRAM (STT-MRAM).

9. The apparatus of claim 1 , comprising the error check information including an error correction value that is based on the first write data and the second write data.

10. A memory controller comprising:
an input/output (I/O) interface to couple with a memory device including a plurality of memory arrays arranged in memory banks; and
command logic comprising circuitry configured to:
send commands to the memory device through the I/O interface; and
send a signal encoded in a write command address strobe (write CAS) command, the signal to specify to the memory device that the commands include successive write commands to a same memory bank of the memory banks of the plurality of memory arrays, the memory device, responsive to the signal, to store first write data of the successive write commands to a buffer of the memory device until a receipt of second write data of the successive write commands, the memory device to calculate error check information based on the first write data and the second write data.

11. The memory controller of claim 10 , comprising the signal encoded in the write CAS command via setting an address bit from among a plurality of address bits for the write CAS command to indicate that the two or more received commands include successive write commands.

12. The memory controller of claim 11 , comprising the memory controller to set the address bit to a value of 1 to indicate that the two or more received commands include successive write commands.

13. The memory controller of claim 10 , comprising the memory device, based on the signal encoded in the write CAS command, buffers the second write data, concurrently with the first write data, until a receipt of third write data of the successive write commands.

14. The memory controller of claim 10 , comprising the memory device to perform a prefetch of bits of data from one or more memory banks of the plurality of memory arrays, a first total number of the bits of data for the prefetch is greater than a second total number of bits of data included in the first write data or a third total number of bits of data included in the second write data.

15. A method comprising:
receiving commands at a memory device;
detecting a signal encoded in a write command address strobe (write CAS) command, the signal to specify that the commands include successive write commands each to a same memory bank of memory banks for a plurality of memory arrays included in the memory device;
responsive to detecting the signal encoded in the write CAS command:
causing first write data of the successive write commands to be stored to a buffer of the memory device until a receipt of second write data of the successive write commands; and
calculating error check information based on the first write data and the second write data.

16. The method of claim 15 , comprising the signal encoded in the write CAS command via setting an address bit from among a plurality of address bits for the write CAS command to indicate that two or more received commands include successive write commands.

17. The method of claim 16 , comprising detecting the signal based on the address bit from among the plurality of address bits being set to a value of 1.

18. The method of claim 15 , further comprising:
responsive to detecting the signal encoded in the write CAS command, causing the second write data to be stored in the buffer, concurrently with the first write data, until a receipt of third write data of the successive write commands.

19. The method of claim 15 , further comprising:
responsive to not detecting the signal encoded in the write CAS command, performing a first read-modify-write operation to store the first write data to at least one of the memory banks of the plurality of memory arrays.

20. The method of claim 15 , comprising:
performing a prefetch of bits of data from one or more memory banks of the plurality of memory arrays, a first total number of the bits of data for the prefetch is greater than a second total number of bits of data included in the first write data or a third total number of bits of data included in the second write data.

21. The method of claim 15 , comprising:
calculating the error check information includes calculating an err

Assignees

• Intel Corp

Inventors

• Bains Kuljit S
• Halbert John B

Classifications

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G11C11/4076

  Timing circuits (for regeneration management G11C11/406) · CPC title

• G11C11/4096

  Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches · CPC title

• G11C11/4093 Primary

  Input/output [I/O] data interface arrangements, e.g. data buffers · CPC title

• G11C7/22

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title