Memory with reduced exposure to manufacturing related data corruption errors

Patent metadata

Field	Value
Publication number	US-11010304-B2
Application number	US-201815865642-A
Country	US
Kind code	B2
Filing date	Jan 9, 2018
Priority date	Jan 9, 2018
Publication date	May 18, 2021
Grant date	May 18, 2021

Abstract

A method performed by a memory is described. The method includes sensing first bits from a first activated column associated with a first sub-word line structure simultaneously with the sensing of second bits from a second activated column associated with a second sub-word line structure. The method also includes providing the first bits at a same first bit location within different read words of a burst read sequence and providing the second bits at a same second bit location within the different read words of the burst read sequence.

First claim

What is claimed:

1. An apparatus, comprising:
a memory chip comprising a) and b) below:
a) at least one macro-array comprising rows of word lines and a plurality of columns, the memory chip further comprising a first column associated with a first sub-word line structure and a second column associated with a second sub-word line structure, the memory chip further comprising a first N:1 serializer circuit between the first column and a first I/O of the memory chip and a second N:1 serializer circuit between the second column and a second I/O of the memory chip, wherein N is an integer, the first and second N:1 serializer circuits to simultaneously serialize stored bits that were simultaneously sensed from the first and second columns respectively so that first stored bits from the first column are presented at the first I/O within different read words of a burst read sequence and second stored bits from the second column are presented at the second I/O within the different read words of the burst read sequence; and,
b) error correction encoding circuitry, the error correction encoding circuitry to generate only one parity bit for each of the different read words of the burst read sequence, and wherein, the memory chip further comprises a third column associated with a third sub-word line structure and a third N:1 serializer circuit, the third N:1 serializer circuit to serialize parity bits for the different read words after the parity bits were simultaneously sensed from the third column and presented to the third N:1 serializer circuit, such that, within any single read word of the different read words, each bit within the single read word is sourced from a different I/O of the memory chip and a different corresponding column of the memory chip, and wherein, a failure of the memory chip is most likely to exist along a same column of the memory chip such that, if the memory chip suffers the failure, only one bit in the single read word is in error.

2. The apparatus of claim 1 wherein the memory chip is a component of a stacked memory chip structure.

3. The apparatus of claim 1 wherein the memory chip is to store an entire cache line.

4. The apparatus of claim 1 wherein the memory chip is a dynamic random access memory.

5. The apparatus of claim 1 wherein the first N:1 serializer circuit is to receive additional stored bits from another activated column so that at least some of the additional stored bits are presented at the first I/O within another group of different read words of the burst read sequence.

6. The apparatus of claim 5 wherein a burst length of the burst read sequence is greater than a number of the stored bits that were sensed from the activated one of the columns.

7. The apparatus of claim 1 wherein each of the stored bits from the first column is presented at the first I/O within the different read words of the burst read sequence.

8. The apparatus of claim 1 wherein pairs of the stored bits from the first and second columns are presented at the first and second I/Os within each of the different read words of the burst read sequence.

9. A computing system, comprising:
a plurality of processing cores;
a main memory controller coupled to the processing cores; and,
a main memory that is coupled to the main memory controller, the main memory composed of memory chips, a memory chip of the memory chips comprising a) and b) below:
a) at least one macro-array comprising rows of word lines and a plurality of columns, the memory chip further comprising a first column associated with a first sub-word line structure and a second column associated with a second sub-word line structure, the memory chip further comprising a first N:1 serializer circuit between the first column and a first I/O of the memory chip and a second N:1 serializer circuit between the second column and a second I/O of the memory chip, wherein N is an integer, the first and second N:1 serializer circuits to simultaneously serialize stored bits that were simultaneously sensed from the first and second columns respectively so that first stored bits from the first column are presented at the first I/O within different read words of a burst read sequence and second stored bits from the second column are presented at the second I/O within the different read words of the burst read sequence; and,
b) error correction encoding circuitry, the error correction encoding circuitry to generate only one parity bit for each of the different read words of the burst read sequence, and wherein, the memory chip further comprises a third column associated with a third sub-word line structure and a third N:1 serializer circuit, the third N:1 serializer circuit to serialize parity bits for the different read word after the parity bits were simultaneously sensed from the third column and presented to the third N:1 serializer circuit, such that, within any single read word of the different read words, each bit within the single read word is sourced from a different I/O of the memory chip and a different corresponding column of the memory chip, and wherein, a failure of the memory chip is most likely to exist along a same column of the memory chip such that, if the memory chip suffers the failure, only one bit in the single read word is in error.

10. The computing system of claim 9 wherein the memory chips are stacked.

11. The computing system of claim 10 wherein a single one of the memory chips is to store a cache line provided by the main memory controller.

12. The computing system of claim 9 wherein the first and second columns are with different micro-arrays of the macro-array.

13. The computing system of claim 12 wherein the different micro-arrays are neighboring micro-arrays.

14. The computing system of claim 9 wherein the first N:1 serializer circuit is to receive additional stored bits from another activated column so that at least some of the additional stored bits are presented at the first I/O within another group of different read words of the burst read sequence.

15. The computing system of claim 14 wherein a burst length of the burst read sequence is greater than a number of the stored bits that were sensed from the another activated column.

16. The computing system of claim 9 wherein each of the stored bits from the first column is presented at the first I/O within the different read words of the burst read sequence.

17. The computing system of claim 16 wherein pairs of the stored bits from the first and second columns are presented at the first and second I/Os within each of the different read words of the burst read sequence.

Assignees

• Intel Corp

Inventors

• Kang Uksong
• Criss Kjersten E
• Agarwal Rajat
• Halbert John B

Classifications

• G06F12/0851

  Cache with interleaved addressing · CPC title

• G06F12/0607

  Interleaved addressing · CPC title

• G11C29/42

  using error correcting codes [ECC] or parity check · CPC title

• G11C11/4091

  Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating · CPC title

• G11C7/10

  Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers · CPC title