Extracting selective information from on-die dynamic random access memory (DRAM) error correction code (ECC)

Patent metadata

Field	Value
Publication number	US-10496473-B2
Application number	US-201715724222-A
Country	US
Kind code	B2
Filing date	Oct 3, 2017
Priority date	Mar 27, 2015
Publication date	Dec 3, 2019
Grant date	Dec 3, 2019

Abstract

Error correction in a memory subsystem includes a memory device generating internal check bits after performing internal error detection and correction, and providing the internal check bits to the memory controller. The memory device performs internal error detection to detect errors in read data in response to a read request from the memory controller. The memory device selectively performs internal error correction if an error is detected in the read data. The memory device generates check bits indicating an error vector for the read data after performing internal error detection and correction, and provides the check bits with the read data to the memory controller in response to the read request. The memory controller can apply the check bits for error correction external to the memory device.

First claim

What is claimed is:

1. A memory controller for performing error correction, comprising:
I/O (input/output) hardware coupled to an associated memory device to send a read command to the associated memory device, the read command including a request that internal check bits be returned with read data, to cause the associated memory device to perform internal error detection to detect errors in read data, selectively perform an internal error correction operation on the read data in response to detection of an error in read data, and generate check bits indicating an error vector for the read data after performance of internal error detection and correction; and the I/O hardware to receive the check bits with the read data in response to the read command; and
an error correction circuit to access the check bits for system error correction external to the associated memory device.

2. The memory controller of claim 1 , wherein the I/O hardware is to send a two cycle read command, with the read command to include the check bits, followed by a read column address strobe (CAS) command to indicate the associated memory device.

3. The memory controller of claim 1 , wherein the I/O hardware is to receive an error vector to indicate no errors in response to detection of no errors in the read data by the associated memory device.

4. The memory controller of claim 1 , wherein the I/O hardware is to receive an error vector to indicate no errors in response to detection of a single bit error in the read data by the associated memory device, wherein internal error detection and correction comprises performance of single bit error correction.

5. The memory controller of claim 1 , wherein the I/O hardware is to receive an error vector to indicate an uncorrected error in response to detection of a multibit error in the read data by the associated memory device, wherein internal error detection and correction comprises detection of the multibit error.

6. The memory controller of claim 1 , wherein the error correction circuit is to access the check bits as metadata for a single device data correction (SDDC) error checking and correction (ECC) operation performed on the read data in connection with parallel read data from an additional memory device.

7. A system comprising:
multiple memory devices; and
a memory controller coupled to the memory devices, the memory controller including
I/O (input/output) hardware coupled to the memory devices to send a read command to a selected memory device, the read command including a request that internal check bits be returned with read data, to cause the selected memory device to perform internal error detection to detect errors in read data, selectively perform an internal error correction operation on the read data in response to detection of an error in read data, and generate check bits indicating an error vector for the read data after performance of internal error detection and correction; and the I/O hardware to receive the check bits with the read data in response to the read command.

8. The system of claim 7 , wherein the I/O hardware is to send a two cycle read command, with the read command to include the check bits, followed by a read column address strobe (CAS) command to indicate the selected memory device.

9. The system of claim 7 , wherein the I/O hardware is to receive an error vector to indicate no errors in response to detection of no errors in the read data by the selected memory device.

10. The system of claim 7 , wherein the I/O hardware is to receive an error vector to indicate no errors in response to detection of a single bit error in the read data by the selected memory device, wherein internal error detection and correction comprises performance of single bit error correction.

11. The system of claim 7 , wherein the I/O hardware is to receive an error vector to indicate an uncorrected error in response to detection of a multibit error in the read data by the selected memory device, wherein internal error detection and correction comprises detection of the multibit error.

12. The system of claim 7 , the memory controller further comprising an error correction circuit, wherein the error correction circuit is to access the check bits as metadata for a single device data correction (SDDC) error checking and correction (ECC) operation performed on the read data in connection with parallel read data from an additional memory device.

13. A method for error correction in a memory subsystem, comprising:
generating a read command for an associated memory device, the read command including a request that internal check bits be returned with read data;
sending the read command to the associated memory device, to cause the associated memory device to perform internal error detection to detect errors in read data, selectively perform an internal error correction operation on the read data in response to detection of an error in read data, and generate check bits indicating an error vector for the read data after performance of internal error detection and correction;
receiving the check bits with the read data in response to the read command; and
accessing the check bits for system error correction external to the associated memory device.

14. The method of claim 13 , wherein sending the read command comprises generating a two cycle read command, with a read command to include the check bits, followed by a read column address strobe (CAS) command to indicate the associated memory device.

15. The method of claim 13 , wherein receiving the check bits comprises receiving an error vector to indicate no errors in response to detection of no errors in the read data by the associated memory device.

16. The method of claim 13 , wherein receiving the check bits comprises receiving an error vector to indicate no errors in response to detection of a single bit error in the read data by the associated memory device, wherein internal error detection and correction comprises performance of single bit error correction.

17. The method of claim 13 , wherein receiving the check bits comprises receiving an error vector to indicate an uncorrected error in response to detection of a multibit error in the read data by the associated memory device, wherein internal error detection and correction comprises detection of the multibit error.

18. The method of claim 13 , wherein accessing the check bits for system error correction comprises accessing the check bits as metadata for a single device data correction (SDDC) error checking and correction (ECC) operation performed on the read data in connection with parallel read data from an additional memory device.

Assignees

• Intel Corp

Inventors

• Das Debaleena
• Nale Bill
• Bains Kuljit S
• Halbert John B

Classifications

• G06F3/064

  Management of blocks · CPC title

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F3/0673

  Single storage device · CPC title

• G06F11/1008 Primary

  in individual solid state devices (G06F11/1004 takes precedence) · CPC title

• G06F11/1076

  Parity data used in redundant arrays of independent storages, e.g. in RAID systems · CPC title