Row hammer monitoring based on stored row hammer threshold value

Patent metadata

Field	Value
Publication number	US-10083737-B2
Application number	US-201715633604-A
Country	US
Kind code	B2
Filing date	Jun 26, 2017
Priority date	Nov 30, 2012
Publication date	Sep 25, 2018
Grant date	Sep 25, 2018

Abstract

Detection logic of a memory subsystem obtains a threshold for a memory device that indicates a number of accesses within a time window that causes risk of data corruption on a physically adjacent row. The detection logic obtains the threshold from a register that stores configuration information for the memory device, and can be a register on the memory device itself and/or can be an entry of a configuration storage device of a memory module to which the memory device belongs. The detection logic determines whether a number of accesses to a row of the memory device exceeds the threshold. In response to detecting the number of accesses exceeds the threshold, the detection logic can generate a trigger to cause the memory device to perform a refresh targeted to a physically adjacent victim row.

First claim

What is claimed is:

1. A memory device comprising:
a memory array including a target row and at least one row physically adjacent to the target row;
a register to store a value to indicate a maximum number of accesses to the target row within a time period; and
a detector to detect when a number of accesses to the target row meets or exceeds the maximum number;
wherein the memory device is to perform a refresh of the row physically adjacent to the target row in response to the number of accesses to meet or exceed the maximum number.

2. The memory device of claim 1 , wherein the at least one row physically adjacent to the target row comprises two victim rows, both to be refreshed in response to the number of accesses to meet or exceed the maximum number.

3. The memory device of claim 1 , wherein the register comprises a dynamic random access memory (DRAM) device mode register to store the value.

4. The memory device of claim 1 , wherein the value comprises an address of an entry in a lookup table of maximum numbers.

5. The memory device of claim 1 , wherein the memory device is to perform the refresh in response to a refresh command from an associated memory controller.

6. The memory device of claim 1 , wherein the memory device is to perform the refresh in response to an activate command from an associated memory controller.

7. The memory device of claim 1 , wherein the detector is to maintain a table of access counts to rows having a highest number of accesses.

8. A system comprising:
a memory controller to send memory access commands; and
a synchronous dynamic random access memory (SDRAM) device including:
a memory array including a target row and at least one row physically adjacent to the target row, wherein the memory access commands include commands to the target row;
a register to store a value to indicate a maximum number of accesses to the target row within a time period; and
a detector to detect when a number of accesses to the target row meets or exceeds the maximum number;
wherein the memory device is to perform a refresh of the row physically adjacent to the target row in response to the number of accesses to meet or exceed the maximum number.

9. The system of claim 8 , wherein the at least one row physically adjacent to the target row comprises two victim rows, both to be refreshed in response to the number of accesses to meet or exceed the maximum number.

10. The system of claim 8 , wherein the register comprises a mode register to store the value.

11. The system of claim 8 , wherein the value comprises an address of an entry in a lookup table of maximum numbers.

12. The system of claim 8 , wherein the SDRAM device is to perform the refresh in response to a refresh command from the memory controller.

13. The system of claim 8 , wherein the SDRAM device is to perform the refresh in response to an activate command from the memory controller.

14. The system of claim 8 , wherein the detector is to maintain a table of access counts to rows having a highest number of accesses.

15. The system of claim 8 , further comprising one or more of:
a multicore processor coupled to the memory controller;
a network interface coupled to SDRAM device; and
a display device configured to provide a user display based on data accessed from the SDRAM device.

16. A method comprising:
accessing, from a register of a memory device, a maximum number that indicates a maximum number of accesses to a target row of the memory device within a time period;
detecting with a detector at the memory device when a number of accesses to a target row meets or exceeds the maximum number; and
performing a refresh of a row physically adjacent to the target row in response to the number of accesses meeting or exceeding the maximum number.

17. The method of claim 16 , wherein accessing the maximum number comprises accessing one of multiple maximum numbers from a lookup table.

18. The method of claim 16 , wherein performing the refresh comprises performing the refresh in response to receipt of a refresh command from an associated memory controller.

19. The method of claim 16 , wherein performing the refresh comprises performing the refresh in response to receipt of an activate command from an associated memory controller.

20. The method of claim 16 , further comprising:
maintaining a table of access counts to rows having a highest number of accesses.

Assignees

• Intel Corp

Inventors

• Bains Kuljit S
• Halbert John B

Classifications

• G06F13/1636

  using refresh · CPC title

• G11C11/406

  Management or control of the refreshing or charge-regeneration cycles · CPC title

• G11C2029/0409

  Online test · CPC title

• G11C11/4078 Primary

  Safety or protection circuits, e.g. for preventing inadvertent or unauthorised reading or writing; Status cells; Test cells (protection of memory contents during checking or testing G11C29/52) · CPC title

• G11C11/40611

  External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh · CPC title