Reduction of power consumption in memory devices during refresh modes

Patent metadata

Field	Value
Publication number	US-10242727-B2
Application number	US-201815983009-A
Country	US
Kind code	B2
Filing date	May 17, 2018
Priority date	Mar 27, 2012
Publication date	Mar 26, 2019
Grant date	Mar 26, 2019

Abstract

Devices, systems, and methods include an active mode to accommodate read/write operations of a memory device and a self-refresh mode to accommodate recharging of voltage levels representing stored data when read/write operations are idle. At least one register source provides a first voltage level and a second voltage level that is less than the first voltage level. With such a configuration, during the active mode, the memory device operates at the first voltage level as provided by the at least one register source, and during the self-refresh mode, the memory device operates at the second voltage level as provided by the at least one register source.

First claim

What is claimed is:

1. A system comprising:
a processor; and
a memory controller communicatively coupled with the processor and a memory device, wherein the memory controller comprises hardware logic to control access to the memory device, including to transmit a command to the memory device to program a register to indicate one of multiple voltage rails for the memory device;
wherein, based at least in part on the register, the memory device is to:
operate from a first voltage rail in a first mode, wherein the first voltage rail is to provide a first DC voltage at a first magnitude, and wherein the first mode is to accommodate read and write operations; and
operate from a second voltage rail in a second mode based at least in part on a register, wherein the second voltage rail is to provide a second DC voltage at a second magnitude that is lower than the first magnitude, and wherein the memory device is to perform self-refresh in the second mode.

2. The system of claim 1 , wherein:
the memory device is to operate from a higher voltage rail in the first mode and operate from a lower voltage rail in the second mode based at least in part on the register and based at least in part on a transition to the second mode.

3. The system of claim 2 , wherein:
the hardware logic of the memory controller is to further trigger the transition of the memory device into the second mode.

4. The system of claim 3 , wherein
the hardware logic to trigger the transition to the second mode is to:
issue a deselect (DES) command to indicate no active read/write operations for the memory device,
transition a clock enable signal low, and
issue self-refresh enable (SRE) command to memory device.

5. The system of claim 3 , wherein:
the memory controller is to cause a transition to the second mode.

6. The system of claim 5 , wherein:
the memory controller to cause the transition to the second mode is to:
issue a deselect (DES) command to indicate no active read/write operations for the memory device,
transition a clock enable signal low, and
issue self-refresh enable (SRE) command to memory device.

7. The system of claim 1 , wherein the processor includes the memory controller.

8. The system of claim 1 , wherein:
the hardware logic is to control access to the memory device in accordance with a DDR (double data rate) standard.

9. The system of claim 1 , wherein:
the hardware logic is to control access to the memory device in accordance with an LPDDR (low power double data rate) standard.

10. The system of claim 1 , wherein:
the hardware logic is to provide a clock enable signal to the memory device, the clock enable signal to trigger entry into the second mode.

11. A system comprising:
a memory controller to control access to a memory device, including to transmit a command to the memory device to program a register to indicate one of multiple voltage rails for the memory device; and
a voltage regulator to supply regulated output voltages to the memory device via a supply line infrastructure, wherein the supply line infrastructure comprises a first voltage rail to provide a first DC voltage at a first magnitude and a second voltage rail to provide a second DC voltage at a second magnitude that is lower than the first magnitude;
wherein, based at least in part on the register, the memory device is to:
operate from the first voltage rail in a first mode, wherein the first mode is to accommodate read and write operations; and
operate from a second voltage rail in a second mode based at least in part on a register, wherein the memory device is to perform self-refresh in the second mode.

12. The system of claim 11 , wherein:
the memory device is to operate from a higher voltage rail in the first mode and operate from a lower voltage rail in the second mode based at least in part on the register and based at least in part on a transition to the second mode.

13. The system of claim 12 , further comprising:
a power supply to provide a voltage to the voltage regulator.

14. The system of claim 11 , wherein:
the memory controller is to control access to the memory device in accordance with a DDR (double data rate) standard.

15. The system of claim 11 , wherein:
the memory controller is to control access to the memory device in accordance with an LPDDR (low power double data rate) standard.

16. The system of claim 11 , wherein:
the memory controller is to provide a clock enable signal to the memory device, the clock enable signal to trigger entry into the second mode.

17. A memory controller comprising:
first hardware logic to control access to a memory device, including to transmit a command to the memory device to program a register to indicate one of multiple voltage rails for the memory device; and
second hardware logic to provide a clock enable signal to the memory device, the clock enable signal to trigger entry into a self-refresh mode;
wherein, based at least in part on the register, the memory device is to:
operate from a first voltage rail in an active mode, wherein the first voltage rail is to provide a first DC voltage at a first magnitude; and
operate from a second voltage rail in the self-refresh mode based at least in part on a register, wherein the second voltage rail is to provide a second DC voltage at a second magnitude that is lower than the first magnitude.

18. The memory controller of claim 17 , wherein:
the memory device is to operate from a higher voltage rail in the active mode and operate from a lower voltage rail in the self-refresh mode based at least in part on the register and based at least in part on the entry into the self-refresh mode.

19. The memory controller of claim 17 , wherein:
the first and second hardware logic is to control access to the memory device in accordance with a DDR (double data rate) standard.

20. The memory controller of claim 17 , wherein:
the first and second hardware logic is to control access to the memory device in accordance with an LPDDR (low power double data rate) standard.

Assignees

• Intel Corp

Inventors

• Cox Christopher E
• Bains Kuljit S
• Halbert John B

Classifications

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C7/08

  Control thereof · CPC title

• G11C16/24

  Bit-line control circuits · CPC title

• G11C2211/4065

  Low level details of refresh operations · CPC title

• G11C7/00

  Arrangements for writing information into, or reading information out from, a digital store (G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413) · CPC title