Precharging and refreshing banks in memory device with bank group architecture

Patent metadata

Field	Value
Publication number	US-10109340-B2
Application number	US-201715639725-A
Country	US
Kind code	B2
Filing date	Jun 30, 2017
Priority date	Feb 28, 2015
Publication date	Oct 23, 2018
Grant date	Oct 23, 2018

Abstract

Memory subsystem refresh management enables commands to access one or more identified banks across different bank groups with a single command. Instead of sending commands identifying a bank or banks in separate bank groups by each bank group individually, the command can cause the memory device to access banks in different bank groups. The command can be a refresh command. The command can be a precharge command.

First claim

What is claimed is:

1. A dynamic random access memory (DRAM) device comprising:
multiple banks of memory addressable by bank group identifier and by bank identifier, wherein a memory access command from an associated controller is to include a bank identifier field and a bank group identifier field;
interface hardware to couple to multiple signal lines of a command and address bus; and
logic capable to identify a signal pattern at the interface hardware as a same bank command including an access command and a bank identifier in the bank identifier field and not including a bank group identifier in the bank group identifier field, the logic to apply the access command to only selected banks in multiple different bank groups in parallel in response to the same bank command.

2. The DRAM device of claim 1 , wherein the same bank command comprises a same bank refresh command.

3. The DRAM device of claim 2 , wherein the logic includes both an internal bank counter to track a refresh count to specific banks, and a global refresh counter.

4. The DRAM device of claim 1 , wherein the same bank command comprises a same bank precharge command.

5. The DRAM device of claim 1 , wherein the same bank command comprises a sequence of a same bank precharge command and a same bank refresh command to access the same bank identifier in different bank groups.

6. The DRAM device of claim 1 , wherein the signal pattern includes a single signal line logic value to differentiate the same bank command from a command directed to bank and bank group.

7. The DRAM device of claim 1 , wherein the DRAM device comprises a memory device compatible with a DDR (double date rate) version 5 (DDR5) standard.

8. A system comprising:
a memory controller to manage refresh of associated memory devices; and
multiple memory devices coupled to the memory controller, wherein a memory device includes
multiple banks of memory addressable by the memory controller by bank group identifier and by bank identifier;
interface hardware to couple to multiple signal lines of a command and address bus; and
logic capable to identify a signal pattern at the interface hardware as a same bank command including an access command and a bank identifier and not including a bank group identifier, the logic to apply the access command to only selected banks in multiple different bank groups in parallel in response to the same bank command.

9. The system of claim 8 , wherein the same bank command comprises a same bank refresh command.

10. The system of claim 9 , wherein the logic includes both an internal bank counter to track a refresh count to specific banks, and a global refresh counter.

11. The system of claim 8 , wherein the same bank command comprises a same bank precharge command.

12. The system of claim 8 , wherein the same bank command comprises a sequence of a same bank precharge command and a same bank refresh command to access the same bank identifier in different bank groups.

13. The system of claim 8 , wherein the signal pattern includes a single signal line logic value to differentiate the same bank command from a command directed to bank and bank group.

14. The system of claim 8 , wherein the memory devices comprise dynamic random access memory (DRAM) devices compatible with a double date rate version 5 (DDR5) standard.

15. The system of claim 8 , further comprising one or more of:
at least one processor communicatively coupled to the memory controller;
a display communicatively coupled to at least one processor; or
a network interface communicatively coupled to at least one processor.

16. A memory controller comprising:
interface hardware to couple over multiple signal lines of a command and address bus to a memory device having multiple banks of memory addressable by the memory controller by bank group identifier and by bank identifier; and
command logic capable to issue a same bank command including selectively setting command and address bits to identify an access command to access only an identified portion of the memory device, the same bank command to identify a bank identifier and to not identify a bank group;
wherein the same bank command is to trigger the memory device to access in parallel only selected banks corresponding to the bank identifier within the memory device for execution of the command, including banks in different bank groups.

17. The memory controller of claim 16 , wherein the same bank command comprises a same bank refresh command.

18. The memory controller of claim 16 , wherein the same bank command comprises a same bank precharge command.

19. The memory controller of claim 16 , wherein the same bank command comprises a sequence of a same bank precharge command and a same bank refresh command to access the same bank identifier in different bank groups.

20. The memory controller of claim 16 , wherein the command logic is to set a signal line of the command and address bus to a logic value to differentiate the same bank command from a command directed to bank and bank group.

Assignees

• Intel Corp

Inventors

• Bains Kuljit S
• Halbert John B
• Bonen Nadav
• Levy Tomer

Classifications

• G11C11/40618 Primary

  Refresh operations over multiple banks or interleaving · CPC title

• G11C11/4087

  Address decoders, e.g. bit - or word line decoders; Multiple line decoders · CPC title

• G11C11/40603 Primary

  Arbitration, priority and concurrent access to memory cells for read/write or refresh operations · CPC title

• G11C11/40611

  External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh · CPC title