Validation of memory on-die error correction code

Patent metadata

Field	Value
Publication number	US-10108512-B2
Application number	US-201615089316-A
Country	US
Kind code	B2
Filing date	Apr 1, 2016
Priority date	Apr 1, 2016
Publication date	Oct 23, 2018
Grant date	Oct 23, 2018

Abstract

Embodiments are generally directed to validation of memory on-die error correction code. An embodiment of a memory device includes one or more memory arrays for the storage of data; control logic to control operation of the memory device; and ECC (error correction code) logic, including ECC correction logic to correct data and ECC generation logic to generate ECC code bits and store the ECC bits in the one or more memory arrays. In a validation mode to validate operation of the ECC logic, the control logic is to allow generation of ECC code bits for a first test value and disable generation of ECC code bits for a second test value.

First claim

What is claimed is:

1. A memory device comprising:
one or more memory arrays for storage of data;
control logic to control operation of the memory device; and
on-die ECC (error correction code) logic, including on-die ECC correction logic to correct data and on-die ECC generation logic to generate ECC code bits and store the ECC bits in the one or more memory arrays;
wherein, in a validation mode in which a host system that is coupled to the memory device desires to confirm that the on-die ECC logic operates correctly, to validate operation of the on-die ECC logic, the control logic is to allow generation of ECC code bits for a first test value and disable generation of ECC code bits for a second test value, wherein the second test value is the first test value with an error, so that the ECC code bits are useable by the on-die ECC logic to correct the error in the second test value and thereby confirm valid operation of the on-die ECC logic.

2. The memory device of claim 1 , wherein the memory device is to write the first test value in a memory array, generate a first set of ECC bits for the first test value, write the second test value in the memory array, and maintain the first set of ECC bits for the second test value.

3. The memory device of claim 2 , wherein the validation mode includes the on-die ECC logic to perform an error check of the second test value using the first set of ECC bits.

4. The memory device of claim 3 , wherein the second test value differs from the first test value by a single flipped bit value, and wherein the validation mode is to validate whether a single bit error represented by the single flipped bit value is corrected.

5. The memory device of claim 4 , wherein the correction of the single bit error is to correct the second test value to be the first test value.

6. The memory device of claim 3 , wherein the second test value differs from the first test value by two flipped bit values, wherein the validation mode is to validate whether either: a double bit error represented by the two flipped bit values is correctly read out; or the double bit error represented by the two flipped bit values is miscorrected into a triple bit error, and a double bit error represented by two bit values of the triple bit error is correctly read out in a data value with a third bit value of the triple bit error not being included in the data value.

7. The memory device of claim 1 , wherein validation of operation of the on-die ECC logic is performed by one of a central processing unit (CPU) of a system, another processor of the system, or a separate testing unit.

8. One or more non-transitory computer-readable storage mediums having stored thereon data representing sequences of instructions that, when executed by one or more processors, cause the one or more processors to perform operations comprising:
writing a first test value in a computer memory;
generating a first set of ECC (error correction code) code bits by an on-die ECC logic of the computer memory in response to the writing of the first test value;
blocking generation of ECC code bits by a memory controller of the computer memory;
writing a second test value in the computer memory, the second test value differing from the first test value by one or more bits;
performing an error check of the second test value based on the first set of ECC code bits; and,
validating operation of the on-die ECC logic based at least in part on the error check of the second test value based on the first set of ECC code bits including verifying that the ECC code bits were useable by the on-die ECC logic to correct the second test value.

9. The one or more mediums of claim 8 , wherein the second test value differs from the first test value by a single bit value; and further comprising instructions that, when executed by the one or more processors, cause the one or more processors to perform operations comprising: validating whether a single bit error represented by the single bit value is corrected.

10. The one or more mediums of claim 9 , wherein validating whether the single bit error is corrected includes determining whether the second test value is corrected to be the first test value.

11. The one or more mediums of claim 8 , wherein the second test value differs from the first test value by a double bit value; and further comprising instructions that, when executed by the one or more processors, cause the one or more processors to perform operations comprising:
validating whether: a double bit error represented by the double bit value is correctly read out, or the double bit error represented by the two flipped bit values is miscorrected into a triple bit error, and a double bit error represented by two bit values of the triple bit error is correctly read out in a data value with a third bit value of the triple bit error not being included in the data value.

12. The one or more mediums of claim 8 , wherein validation of operation of the on-die ECC logic is performed by one of a central processing unit (CPU) of a system, another processor of the system, or a separate testing unit.

13. A computing system comprising:
one or more processors; and
synchronous dynamic random access memory (SDRAM) for storage of data, the SDRAM including a memory device having:
one or more memory arrays for the storage of data,
control logic to control operation of the memory device, and
on-die ECC (error correction code) logic, including on-die ECC correction logic to correct data and on-die ECC generation logic to generate ECC code bits and store the ECC bits in the one or more memory arrays;
wherein, in a validation mode in which a host system that is coupled to the memory device desires to confirm that the on-die ECC logic operates correctly, to validate operation of the on-die ECC logic, the control logic is to allow generation of ECC code bits for a first test value and disable generation of ECC code bits for a second test value, wherein the second test value is the first test value with an error, so that the ECC code bits are useable by the on-die ECC logic to correct the error in the second test value and thereby confirm valid operation of the on-die ECC logic.

14. The computing system of claim 13 , wherein the memory device is to write the first test value in a memory array, generate a first set of ECC bits for the first test value, write the second test value in the memory array, and maintain the first set of ECC bits for the second test value.

15. The computing system of claim 14 , wherein the validation mode includes the on-die ECC logic to perform an error check of the second test value using the first set of ECC bits.

16. The computing system of claim 15 , wherein the second test value differs from the first test value by a single flipped bit value, and wherein the validation mode is to validate whether a single bit error represented by the single flipped bit value is corrected.

17. The computing system of claim 16 , wherein the correction of the single bit error is to correct the second test value to be the first test value.

18. The computing system of claim 15 , wherein the second test value differs from the first test value by two flipped bit values, wherein the validation mode is to validate whether either: a double bit error represented by the two flipped bit values is correctly read out; or the double bit error represented by the two flipped bit values is miscorrected into a triple bit error, and a double bit error represented by two bit values of the triple bit error is correctly read out in a data val

Assignees

• Intel Corp

Inventors

• Halbert John B
• Bains Kuljit S

Classifications

• G06F11/1068

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• G06F11/2215 Primary

  to test error correction or detection circuits · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G06F11/008

  Reliability or availability analysis · CPC title

• G11C29/02

  Detection or location of defective auxiliary circuits, e.g. defective refresh counters · CPC title