Memory device error check and scrub mode and error transparency

Patent metadata

Field	Value
Publication number	US-10810079-B2
Application number	US-201816178528-A
Country	US
Kind code	B2
Filing date	Nov 1, 2018
Priority date	Aug 28, 2015
Publication date	Oct 20, 2020
Grant date	Oct 20, 2020

Abstract

An error check and scrub (ECS) mode enables a memory device to perform error checking and correction (ECC) and count errors. An associated memory controller triggers the ECS mode with a trigger sent to the memory device. The memory device includes multiple addressable memory locations, which can be organized in segments such as wordlines. The memory locations store data and have associated ECC information. In the ECS mode, the memory device reads one or more memory locations and performs ECC for the one or more memory locations based on the ECC information. The memory device counts error information including a segment count indicating a number of segments having at least a threshold number of errors, and a maximum count indicating a maximum number of errors in any segment.

First claim

What is claimed is:

1. A dynamic random access memory (DRAM) device, comprising:
a memory array including multiple rows;
error checking and correction (ECC) logic to detect and correct bit errors;
a first register as a row error counter to indicate a total number of code word errors detected in an error check and scrub (ECS) mode where the DRAM device is to internally read data, correct single bit errors in the rows of the memory array with the ECC logic, and write corrected data back to the memory array; and
a second register as an errors per row counter to indicate an address of a row with a largest number of code word errors in the ECS mode.

2. The DRAM device of claim 1 , wherein the first and second registers comprise Mode Registers.

3. The DRAM device of claim 1 , further comprising:
an input/output (I/O) interface to receive a command to set a bit of a mode register to enter the ECS mode.

4. The DRAM device of claim 3 , wherein in the ECS mode, the I/O interface is to receive a command sequence including an ECS entry command (ECS), an Activate command (ACT), a Write command (WR), and a Precharge command (PRE).

5. The DRAM device of claim 1 , further comprising:
a counter to count a number of errors for a row being checked, compare the count to a stored highest value, and write an address of the row being checked to the second register if the count is larger than the stored highest value.

6. The DRAM device of claim 1 , wherein the DRAM device includes a synchronous dynamic random access memory (SDRAM) device compatible with a double data rate (DDR) standard.

7. The DRAM device of claim 1 , wherein the first register is to store only a number of errors detected in excess of a threshold.

8. The DRAM device of claim 1 , wherein the DRAM device is to write corrected data back to a same address of the memory array in which a single bit error was detected.

9. A dynamic random access memory (DRAM) device, comprising:
a memory array including multiple rows;
error checking and correction (ECC) logic to detect and correct bit errors;
a first register as a row error counter to indicate a number of rows that have at least one code word error detected in an error check and scrub (ECS) mode where the DRAM device is to internally read data, correct single bit errors in the rows of the memory array with the ECC logic, and write corrected data back to the memory array; and
a second register as an errors per row counter to indicate an address of a row with a largest number of code word errors in the ECS mode.

10. The DRAM device of claim 9 , wherein the first and second registers comprise Mode Registers.

11. The DRAM device of claim 9 , further comprising:
an input/output (I/O) interface to receive a command to set a bit of a mode register to enter the ECS mode.

12. The DRAM device of claim 11 , wherein in the ECS mode, the I/O interface is to receive a command sequence including an ECS entry command (ECS), an Activate command (ACT), a Write command (WR), and a Precharge command (PRE).

13. The DRAM device of claim 9 , wherein the DRAM device includes a synchronous dynamic random access memory (SDRAM) device compatible with a double data rate (DDR) standard.

14. The DRAM device of claim 9 , wherein the first register is to store only a number of errors detected in excess of a threshold.

15. The DRAM device of claim 9 , wherein the DRAM device is to write corrected data back to a same address of the memory array in which a single bit error was detected.

16. A memory controller comprising:
a hardware interface to couple to a memory device having a memory array including multiple rows; and
command logic to generate
a first command to read a row error count from a first register of the memory device, the row error count to indicate a total number of code word errors, the row error count to result from an error check and scrub (ECS) mode where the memory device is to internally read data, correct single bit errors in the rows of the memory array, and write corrected data back to the memory array; and
a second command to read an errors per row counter value from a second register of the memory device, the errors per row count to indicate an address of a row with a largest number of code word errors detected in the ECS mode.

17. The memory controller of claim 16 , wherein the first and second registers comprise Mode Registers of the memory device.

18. The memory controller of claim 16 , wherein the command logic is to generate a command to set a bit of a mode register of the memory device to cause the memory device to enter the ECS mode.

19. The memory controller of claim 18 , wherein when the memory device is in the ECS mode, the command logic is to generate a command sequence including an ECS entry command (ECS), an Activate command (ACT), a Write command (WR), and a Precharge command (PRE).

20. The memory controller of claim 16 , wherein the errors per row counter value is to result from a counter to count a number of errors for a row being checked, a comparison of the count to a stored highest value, and writing of an address of the row being checked to the second register if the count is larger than the stored highest value.

21. The memory controller of claim 16 , wherein the command logic is to generate a command to cause the memory device to enter the ECS mode only after all banks of the memory device have been precharged and are in an idle state.

22. A memory controller comprising:
a hardware interface to couple to a memory device having a memory array including multiple rows; and
command logic to generate
a first command to read a row error count from a first register of the memory device, the row error count to indicate a number of rows that have at least one code word error, the row error count to result from an error check and scrub (ECS) mode where the memory device is to internally read data, correct single bit errors in the rows of the memory array, and write corrected data back to the memory array; and
a second command to read an errors per row counter value from a second register of the memory device, the errors per row count to indicate an address of a row with a largest number of code word errors detected in the ECS mode.

23. The memory controller of claim 22 , wherein the first and second registers comprise Mode Registers of the memory device.

24. The memory controller of claim 22 , wherein the command logic is to generate a command to set a bit of a mode register of the memory device to cause the memory device to enter the ECS mode.

25. The memory controller of claim 24 , wherein when the memory device is in the ECS mode, the command logic is to generate a command sequence including an ECS entry command (ECS), an Activate command (ACT), a Write command (WR), and a Precharge command (PRE).

26. The memory controller of claim 22 , wherein the errors per row counter value is to result from a counter to count a number of errors for a row being checked, a comparison of the count to a stored highest value, and writing of an address of the row being checked to the second register if the count is larger than the stored highest value.

27. A system, comprising:
a memory controller; and
a dynamic random access memory (DRAM) device coupled to the memory controller, the DRAM device comprising:
a memory array including multiple rows;
error checking and correction

Assignees

• Intel Corp

Inventors

• Halbert John B
• Bains Kuljit S

Classifications

• G11C29/42 Primary

  using error correcting codes [ECC] or parity check · CPC title

• H03M13/095

  Error detection codes other than CRC and single parity bit codes · CPC title

• G06F11/1048 Primary

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• H03M13/6566

  Implementations concerning memory access contentions · CPC title