Stacked memory chip device with enhanced data protection capability

Patent metadata

Field	Value
Publication number	US-10459809-B2
Application number	US-201715640182-A
Country	US
Kind code	B2
Filing date	Jun 30, 2017
Priority date	Jun 30, 2017
Publication date	Oct 29, 2019
Grant date	Oct 29, 2019

Abstract

A stacked memory chip device is described. The stacked memory chip device includes a plurality of stacked memory chips. The stacked memory chip device includes read/write logic circuitry to service read/write requests for cache lines kept within the plurality of stacked memory chips. The stacked memory chip device includes data protection circuitry to store information to protect substantive data of cache lines in the plurality of stacked memory chips, where, the information is kept in more than one of the plurality of stacked memory chips, and where, any subset of the information that protects respective substantive information of a particular one of the cache lines is not stored in a same memory chip with the respective substantive information.

First claim

The invention claimed is:

1. A stacked memory chip device, comprising:
a plurality of stacked memory chips;
read/write logic circuitry to service read/write requests for cache lines kept within the plurality of stacked memory chips;
data protection circuitry to store information to protect substantive data of cache lines in the plurality of stacked memory chips, where, the information is kept in more than one of the plurality of stacked memory chips, and where, any subset of the information that protects respective substantive data of a particular one of the cache lines is not stored in a same memory chip with the respective substantive data, the information to protect the substantive data of the cache lines being one of mirroring information and ECC information.

2. The stacked memory chip device of claim 1 where the information is to be stored at row/column granularity.

3. The stacked memory chip device of claim 1 where the information is to be stored at bank granularity.

4. The stacked memory chip device of claim 1 wherein the information is to be stored in a region of the plurality of memory chips that is reserved for storage of respective information to protect respective substantive data of multiple cache lines.

5. The stacked memory chip device of claim 4 wherein the information is to be stored in a channel that is reserved for storage of respective information to protect respective substantive data of multiple cache lines.

6. The stacked memory chip device of claim 4 wherein the information is to be stored in a particular one of the stacked memory chips that is reserved for storage of respective information to protect substantive data of multiple cache lines.

7. The stacked memory chip device of claim 1 wherein the stacked memory chips are DRAM memory chips.

8. The stacked memory chip device of claim 1 wherein the stacked memory chips are non-volatile system memory chips.

9. The stacked memory chip device of claim 1 wherein the information is mirroring information.

10. The stacked memory chip device of claim 1 wherein the information is error correction coding (ECC) information.

11. The stacked memory chip device of claim 1 further comprising error correction coding circuitry to determine said information from said substantive data.

12. The stacked memory chip device of claim 1 wherein the stacked memory chips are DRAM memory chips.

13. The stacked memory chip device of claim 1 wherein the stacked memory chips are non-volatile system memory chips.

14. A computing system, comprising:
a plurality of processing cores;
a system memory controller coupled to the plurality of processing cores;
a system memory coupled to the system memory controller, the system memory comprising a stacked memory chip device, the stacked memory chip device comprising a), b) and c) below:
a) a plurality of stacked memory chips;
b) read/write logic circuitry to service read/write requests for cache lines kept within the plurality of stacked memory chips;
c) data protection circuitry to store information to protect substantive data of cache lines in the plurality of stacked memory chips, where, the information is kept in more than one of the plurality of stacked memory chips, and where, any subset of the information that protects respective substantive data of a particular one of the cache lines is not stored in a same memory chip with the respective substantive data, the information to protect the substantive data of the cache lines being one of mirroring information and ECC information.

15. The computing system of claim 14 where the information is to be stored at any of:
row/column granularity;
bank granularity.

16. The stacked memory chip device of claim 14 wherein the information is to be stored in a region of the plurality of stacked memory chips that is reserved for storage of respective information to protect respective substantive data of multiple cache lines.

17. The stacked memory chip device of claim 16 wherein the information is to be stored in a particular one of the stacked memory chips that is reserved for storage of respective information to protect substantive data of multiple cache lines.

18. A method, comprising:
receiving cache lines to be written into system memory space comprising multiple stacked memory chips;
storing information that protects substantive data of the cache lines in more than one of the stacked memory chips, where, any subset of the information that protects respective substantive data of a particular one of the cache lines is not stored in a same memory chip with the respective substantive data, the information to protect the substantive data of the cache lines being one of mirroring information and ECC information.

19. The method of claim 18 wherein the information is mirroring information.

20. The method of claim 18 wherein the information is ECC information.

Assignees

• Intel Corp

Inventors

• Alameer Hussein
• Kang Uksong
• Criss Kjersten E
• Agarwal Rajat
• Wu Wei
• Halbert John B

Classifications

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/00

  Package configurations · CPC title

• G11C2029/0411

  Online error correction · CPC title

• G11C5/04

  Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title

• G11C29/74

  using duplex memories, i.e. using dual copies · CPC title