On-die ECC with error counter and internal address generation

Patent metadata

Field	Value
Publication number	US-10949296-B2
Application number	US-201715681387-A
Country	US
Kind code	B2
Filing date	Aug 20, 2017
Priority date	May 31, 2015
Publication date	Mar 16, 2021
Grant date	Mar 16, 2021

Abstract

A memory subsystem enables managing error correction information. A memory device internally performs error detection for a range of memory locations, and increments an internal count for each error detected. The memory device includes ECC logic to generate an error result indicating a difference between the internal count and a baseline number of errors preset for the memory device. The memory device can provide the error result to an associated host of the system to expose only a number of errors accumulated without exposing internal errors from prior to incorporation into a system. The memory device can be made capable to generate internal addresses to execute commands received from the memory controller. The memory device can be made capable to reset the counter after a first pass through the memory area in which errors are counted.

First claim

What is claimed is:

1. A random access memory (RAM) device, comprising:
a memory array;
an error count register to store an error result for access by an associated memory controller; and
error checking and correction (ECC) circuitry to perform internal ECC operations to check and correct errors for multiple rows of the memory array, where the ECC circuitry is to generate address information internally to address the multiple rows for the internal ECC operations, the ECC circuitry including a counter to accumulate an error count, the error count to be incremented in response to detection of an error in any of the multiple rows, wherein the ECC circuitry is to generate the error result as a difference between the accumulated error count and a non-zero error threshold and store the error result in the error count register, wherein the error threshold represents a preset number of errors to exclude from the error result.

2. The RAM device of claim 1 , wherein the ECC circuitry is to perform the internal ECC operations in response to initiation of error detection testing by the RAM device.

3. The RAM device of claim 1 , wherein the ECC circuitry is to perform the internal ECC operations to check and correct errors for the multiple rows of the memory array within a bounded address space.

4. The RAM device of claim 1 , wherein the ECC circuitry is to perform the internal ECC operations for all rows of the memory array.

5. The RAM device of claim 1 , wherein the ECC circuitry is to automatically reset the accumulated error count in response to detection of an address rollover to a previously-tested address.

6. The RAM device of claim 1 , wherein the error result is to indicate a number of errors since deployment into a system.

7. The RAM device of claim 1 , wherein error threshold comprises a number of errors configured for the RAM device during a manufacturing process.

8. The RAM device of claim 1 , wherein the RAM device comprises a volatile dynamic random access memory (DRAM) device.

9. The RAM device of claim 1 , wherein the RAM device comprises a nonvolatile RAM device.

10. A system comprising:
a memory controller; and
multiple random access memory (RAM) devices coupled in parallel, wherein a RAM device includes
a memory array;
error checking and correction (ECC) circuitry to perform internal ECC operations to check and correct errors for multiple rows of the memory array, where the ECC circuitry is to generate address information internally to address the multiple rows for the internal ECC operations, the ECC circuitry including a counter to accumulate an error count, the error count to be incremented in response to detection of an error in any of the multiple rows, wherein the ECC circuitry is to generate an error result as a difference between the accumulated error count and a non-zero error threshold, wherein the error threshold represents a preset number of errors to exclude from the error result; and

a register to store the error result for access by an associated memory controller;
wherein the RAM devices provide internal error correction on data independent of error correction based on check bits provided by the memory controller.

11. The system of claim 10 , wherein the ECC circuitry is to perform the internal ECC operations in response to initiation of error detection testing by the RAM device.

12. The system of claim 10 , wherein the ECC circuitry is to automatically reset the accumulated error count in response to detection of an address rollover to a previously-tested address.

13. The system of claim 10 , further comprising one or more of:
at least one processor communicatively coupled to the memory controller;
a display communicatively coupled to at least one processor; or
a network interface communicatively coupled to at least one processor.

14. The system of claim 10 , wherein the RAM devices comprise volatile dynamic random access memory (DRAM) devices.

15. The system of claim 10 , wherein the RAM devices comprise nonvolatile RAM devices.

16. The system of claim 10 , wherein the memory controller is to apply error results from the multiple RAM devices for system-level ECC across the multiple RAM devices.

17. A memory controller, comprising:
a hardware interface to receive data from multiple memory devices, wherein a memory device includes on-die error checking and correction (ECC) circuitry to perform internal ECC operations to check and correct errors for multiple rows of the memory device, where the ECC circuitry is to generate address information internally to address the multiple rows for the internal ECC operations, the ECC circuitry having a counter to accumulate an error count, the error count to be incremented in response to detection of an error in any of the multiple rows of the memory device, wherein the on-die ECC circuitry is to generate an error result to store in an error count register of the memory device as a difference between the accumulated error count and a non-zero error threshold, wherein the error threshold represents a preset number of errors to exclude from the error result; and
system-level ECC circuitry to perform ECC operations for the multiple memory devices, the system-level ECC circuitry to perform error correction based on check bits provided by the memory controller to the multiple memory devices and error counts from the multiple memory devices.

18. The memory controller of claim 17 , wherein the hardware interface is to send a command to a mode register of the memory device to cause the memory device to perform an error check and scrub with the memory device to generate address information for the error check and scrub.

19. The memory controller of claim 18 , wherein the memory device is to automatically reset the accumulated error count in response to detection of an address rollover to a previously-tested address.

20. The memory controller of claim 17 , wherein the baseline number of errors comprises a number of errors detected during manufacturing testing of the memory device.

Assignees

• Intel Corp

Inventors

• Halbert John B
• Bains Kuljit S

Classifications

• G11C2029/0411

  Online error correction · CPC title

• G11C29/56008

  Error analysis, representation of errors · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G11C29/44

  Indication or identification of errors, e.g. for repair · CPC title

• G11C29/42

  using error correcting codes [ECC] or parity check · CPC title