Semiconductor structure having stacked gates and method of manufacture thereof
US-12568651-B2 · Mar 3, 2026 · US
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Gutwin Paul patents
Gutwin Paul is listed as an inventor on 37 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Gutwin Paul |
| Total patents | 37 |
| First publication | Apr 21, 2022 |
| Latest publication | Mar 3, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Inverted cross-couple for top-tier FET for multi-tier gate-on-gate 3DI
US-12557377-B2 · Feb 17, 2026 · US
Inverted top-tier FET for multi-tier gate-on-gate 3-dimension integration (3Di)
US-12446291-B2 · Oct 14, 2025 · US
Tapered device for lateral gate all around devices
US-12414367-B2 · Sep 9, 2025 · US
Self-aligned method for vertical recess for 3D device integration
US-12336274-B2 · Jun 17, 2025 · US
Wiring in diffusion breaks in an integrated circuit
US-2025120174-A1 · Apr 10, 2025 · US
Backside power gating
US-2025112122-A1 · Apr 3, 2025 · US
Interdigitated device stack
US-12224281-B2 · Feb 11, 2025 · US
Wiring in diffusion breaks in an integrated circuit
US-12218135-B2 · Feb 4, 2025 · US
Inter-tier power delivery network (PDN) for dense gate-on-gate 3D logic integration
US-12176293-B2 · Dec 24, 2024 · US
Recent patents
Latest publications not already listed above.
Integrated high efficiency transistor cooling
US-2024347422-A1 · Oct 17, 2024 · US
Integrated high efficiency transistor cooling
US-12051638-B2 · Jul 30, 2024 · US
Beol contact metals for 2d transistors
US-2024222461-A1 · Jul 4, 2024 · US
Inter-level handshake for dense 3D logic integration
US-12002862-B2 · Jun 4, 2024 · US
Power-tap pass-through to connect a buried power rail to front-side power distribution network
US-11961802-B2 · Apr 16, 2024 · US
Double cross-couple for two-row flip-flop using CFET
US-11923364-B2 · Mar 5, 2024 · US
Multi-tier backside power delivery network for dense gate-on-gate 3D logic
US-11830852-B2 · Nov 28, 2023 · US
Method of 3D logic fabrication to sequentially decrease processing temperature and maintain material thermal thresholds
US-11764113-B2 · Sep 19, 2023 · US
Three-dimensional semiconductor device
US-11764266-B2 · Sep 19, 2023 · US
Three-dimensional memory cell structure
US-11723187-B2 · Aug 8, 2023 · US
Wiring in Diffusion Breaks in an Integrated Circuit
US-2023223404-A1 · Jul 13, 2023 · US
Three-dimensional semiconductor device
US-2023100332-A1 · Mar 30, 2023 · US
Tapered device for lateral gate all around devices
US-2023078381-A1 · Mar 16, 2023 · US
Integrated high efficiency gate on gate cooling
US-11581242-B2 · Feb 14, 2023 · US
Self-aligned method for vertical recess for 3d device integration
US-2023036597-A1 · Feb 2, 2023 · US
Independent gate contacts for cfet
US-2023017350-A1 · Jan 19, 2023 · US
Semiconductor structure having stacked gates and method of manufacture thereof
US-2022416048-A1 · Dec 29, 2022 · US
Stacked three-dimensional field-effect transistors
US-11532708-B2 · Dec 20, 2022 · US
Inverted cross-couple for top-tier fet for multi-tier gate-on-gate 3di
US-2022367461-A1 · Nov 17, 2022 · US
Three-dimensional memory cell structure
US-2022302121-A1 · Sep 22, 2022 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Tokyo Electron Ltd | 35 |
| Intel Corp | 2 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10D30/6735 | 33 |
| H10D84/038 | 33 |
| H10D88/00 | 33 |
| H10D30/6757 | 31 |
| H10D84/85 | 31 |