Inverted top-tier FET for multi-tier gate-on-gate 3-dimension integration (3Di)

Patent metadata

Field	Value
Publication number	US-12446291-B2
Application number	US-202117542024-A
Country	US
Kind code	B2
Filing date	Dec 3, 2021
Priority date	Feb 19, 2021
Publication date	Oct 14, 2025
Grant date	Oct 14, 2025

Abstract

Aspects of the present disclosure provide a multi-tier semiconductor structure. For example, the multi-tier semiconductor structure can include a first semiconductor device tier that includes first semiconductor devices. A first signal wiring structure can be formed over and electrically connected to the first semiconductor device tier. An insulator layer can be formed over the first signal wiring structure. A second semiconductor device tier can be formed over the insulator layer, the second semiconductor device tier including second semiconductor devices. A second signal wiring structure can be formed over and electrically connected to the second semiconductor device tier. An inter-tier via can be formed vertically through the insulator layer and electrically connecting the second signal wiring structure to the first signal wiring structure. The first semiconductor device tier, the second semiconductor device tier and the inter-tier via can be formed monolithically.

First claim

What is claimed is:

1. A multi-tier semiconductor structure, comprising:
a first semiconductor device tier that includes first semiconductor devices;
a first signal wiring structure formed over and electrically connected to the first semiconductor device tier;
an insulator layer formed over the first signal wiring structure;
a second semiconductor device tier formed over the insulator layer, the second semiconductor device tier including second semiconductor devices;
a second signal wiring structure formed over and electrically connected to the second semiconductor device tier;
a second power rail that is formed over and electrically connected to the second semiconductor device tier; and
an inter-tier via formed vertically through the insulator layer and electrically connecting the second signal wiring structure to the first signal wiring structure,
wherein the inter-tier via has two opposing ends that are in direct contact with the second signal wiring structure and the first signal wiring structure, respectively,
the inter-tier via is electrically connected to a lower surface of the second signal wiring structure in a region that is above the second semiconductor device tier, and
the second power rail does not horizontally overlap with the region.

2. The multi-tier semiconductor structure of claim 1 , wherein the inter-tier via is formed in a diffusion break region that vertically isolates neighboring ones of the second semiconductor devices.

3. The multi-tier semiconductor structure of claim 2 , wherein the second semiconductor device tier includes a dummy poly, and the inter-tier via is aligned with the dummy poly.

4. The multi-tier semiconductor structure of claim 1 , further comprising a substrate, wherein the first semiconductor device tier is formed over the substrate.

5. The multi-tier semiconductor structure of claim 4 , further comprising a first power rail that is buried in the substrate and electrically connected to the first semiconductor device tier.

6. The multi-tier semiconductor structure of claim 1 , wherein the first semiconductor devices are vertically stacked over one another and/or the second semiconductor devices are vertically stacked over one another.

7. The multi-tier semiconductor structure of claim 6 , wherein the second semiconductor devices include field effect transistors (FETs).

8. The multi-tier semiconductor structure of claim 1 , wherein the first semiconductor device tier, the second semiconductor device tier and the inter-tier via are formed monolithically.

9. The multi-tier semiconductor structure of claim 1 , further comprising a contact that is vertically formed to electrically connect the second semiconductor device tier to the second signal wiring structure.

10. The multi-tier semiconductor structure of claim 1 , further comprising a contact that is formed vertically through the insulator layer to electrically connect the second semiconductor device tier to the first signal wiring structure.

11. The multi-tier semiconductor structure of claim 10 , wherein the contact includes a gate contact that electrically connects a gate region of one of the second semiconductor devices of the second semiconductor device tier to the first signal wiring structure.

12. The multi-tier semiconductor structure of claim 10 , wherein the contact includes a source/drain contact that electrically connects a source/drain region of one of the second semiconductor devices of the second semiconductor device tier to the first signal wiring structure.

13. The multi-tier semiconductor structure of claim 1 , wherein the insulator layer includes a silicon-on-insulator (SoI) layer.

14. A method of fabricating a multi-tier semiconductor structure, the method comprising:
forming a first semiconductor device tier, the first semiconductor device tier including first semiconductor devices;
forming a first signal wiring structure over the first semiconductor device tier and electrically connecting the first signal wiring structure to the first semiconductor device tier;
forming an insulator layer over the first signal wiring structure;
forming a second semiconductor device tier over the insulator layer, the second semiconductor device tier including second semiconductor devices;
forming a second signal wiring structure over the second semiconductor device tier and electrically connecting the second signal wiring structure to the second semiconductor device tier; and
forming an inter-tier via vertically through the insulator layer to electrically connect the second signal wiring structure to the first signal wiring structure,
wherein the inter-tier via has two opposing ends that are in direct contact with the second signal wiring structure and the first signal wiring structure, respectively,
the inter-tier via is electrically connected to a lower surface of the second signal wiring structure in a region that is above the second semiconductor device tier; and
forming a second power rail over and electrically connecting the second power rail to the second semiconductor device tier,
wherein the second power rail does not horizontally overlap with the region.

15. The method of claim 14 , wherein forming an inter-tier via includes forming an inter-tier via in a diffusion break region that vertically isolates neighboring ones of the second semiconductor devices.

16. The method of claim 15 , wherein the second semiconductor device tier includes a dummy poly, and the inter-tier via is aligned with the dummy poly.

17. The method of claim 14 , wherein the first semiconductor device tier, the second semiconductor device tier and the inter-tier via are formed monolithically.

18. The method of claim 14 , further comprising forming a contact vertically through the insulator layer to electrically connect the second semiconductor device tier to the first signal wiring structure.

Assignees

• Tokyo Electron Ltd

Inventors

• Chanemougame Daniel
• Liebmann Lars
• Smith Jeffrey
• Gutwin Paul
• Xu Xiaoqing

Classifications

• H10W20/481

  on the rear surfaces of the wafers or substrates · CPC title

• H10P14/3452

  Microstructure · CPC title

• H10W20/427

  Power or ground buses · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10D84/0167

  Manufacturing their channels · CPC title