Power-tap pass-through to connect a buried power rail to front-side power distribution network

Patent metadata

Field	Value
Publication number	US-11961802-B2
Application number	US-202117328236-A
Country	US
Kind code	B2
Filing date	May 24, 2021
Priority date	Dec 4, 2020
Publication date	Apr 16, 2024
Grant date	Apr 16, 2024

Abstract

A semiconductor device includes a device plane including an array of cells each including a transistor device. The device plane is formed on a working surface of a substrate and has a front side and a backside opposite the front side. A signal wiring structure is formed on the front side of the device plane. A front-side power distribution network (FSPDN) is positioned on the front side of the device plane. A buried power rail (BPR) is disposed below the device plane on the backside of the device plane. A power tap structure is formed in the device plane. The power tap structure electrically connects the BPR to the FSPDN and electrically connects the BPR to at least one of the transistor devices to provide power to the at least one of the transistor devices.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first device plane including an array of cells each including a transistor device, the first device plane formed on a working surface of a substrate, the first device plane having a front side and a backside opposite the front side;
a signal wiring structure formed on the front side of the first device plane;
a front-side power distribution network (FSPDN) positioned on the front side of the first device plane;
a first buried power rail (BPR) disposed below the first device plane on the backside of the first device plane; and
a power tap structure in the first device plane, the power tap structure electrically connecting the first BPR to the FSPDN and electrically connecting the first BPR to at least one of the transistor devices to provide power to the at least one of the transistor devices.

2. The semiconductor device of claim 1 , wherein the array of cells comprises a logic cell, and the FSPDN comprises a power tap track on a cell boundary of the logic cell, the power tap track disposed in a first wiring layer (M0).

3. The semiconductor device of claim 2 , wherein the power tap structure comprises:
an LI structure;
a top contact that is disposed on the front side of the LI structure and contacts the power tap track; and
a power via that is disposed on the backside of the LI structure and contacts the first BPR.

4. The semiconductor device of claim 3 , wherein the LI structure extends in a horizontal direction along the working surface of the substrate so as to contact the transistor device of the logic cell.

5. The semiconductor device of claim 4 , wherein:
the FSPDN is electrically connected to the first BPR via the power tap structure, and
the first BPR is configured to provide power to the transistor device via the LI structure.

6. The semiconductor device of claim 1 , wherein the array of cells comprises a pair of adjacent logic cells, and the first BPR is disposed on a common cell boundary of the pair of adjacent logic cells and is configured to function as a common BPR.

7. The semiconductor device of claim 6 , wherein the FSPDN comprises a common power tap track on the common cell boundary, the common power tap track disposed in a first wiring layer (M0).

8. The semiconductor device of claim 7 , wherein the power tap structure comprises:
a common LI structure within the pair of adjacent logic cells;
a common top contact that is disposed on the front side of the common LI structure and contacts the common power tap track; and
a common power via that is disposed on the backside of the common LI structure and contacts the first BPR.

9. The semiconductor device of claim 8 , wherein:
the common LI structure extends across the common cell boundary in a horizontal direction along the working surface of the substrate,
one end of the common LI structure contacts a transistor device of one logic cell of the pair of adjacent logic cells, and
another end of the common LI structure contacts a transistor device of the other logic cell of the pair of adjacent logic cells.

10. The semiconductor device of claim 9 , wherein:
the FSPDN is electrically connected to the first BPR via the power tap structure, and
the power tap structure is configured to function as a common power tap structure in order for the first BPR to provide power to the transistor devices on the two ends of the common LI structure.

11. The semiconductor device of claim 9 , wherein:
the transistor devices include complementary field-effect transistors (CFETs), each having an N-type device over a P-type device,
the P-type devices are configured to connect to the first BPR for V DD via the common LI structure, and
the N-type devices in each adjacent logic cell are configured to connect to separate BPRs for V SS via separate power tap structures.

12. The semiconductor device of claim 1 , wherein the array of cells comprises a pair of adjacent logic cells, and only one logic cell of the pair of adjacent logic cells includes a power tap structure while the other logic cell of the pair of adjacent logic cells has a signal connection that is positioned away from an outer M0 track.

13. The semiconductor device of claim 1 , further comprising a backside power distribution network (BSPDN) positioned below the first BPR on the backside of the first device plane, wherein the first BPR is electrically connected to the BSPDN via a bottom through-silicon via (TSV).

14. The semiconductor device of claim 1 , further comprising a power tap cell in the array of cells, the power tap cell providing power to the transistor device by electrically connecting the transistor device to the first BPR.

15. The semiconductor device of claim 14 , wherein the power tap cell further comprises a conductive structure that connects the first BPR to the FSPDN.

16. The semiconductor device of claim 1 , further comprising:
a second device plane positioned below the first BPR;
a second BPR below the second device plane; and
a BSPDN below the second BPR, wherein the second BPR is electrically connected to the BSPDN and is configured to provide power to a device in the second device plane.

17. A method of microfabrication, comprising:
forming a device plane including an array of cells each including a transistor device, the device plane formed on a working surface of a substrate, the device plane having a front side and a backside opposite the front side;
forming a buried power rail (BPR) that is positioned below the device plane on the backside of the device plane;
forming a signal wiring structure on the front side of the device plane;
forming a front-side power distribution network (FSPDN) on the front side of the device plane; and
forming a power tap structure in the device plane, the power tap structure electrically connecting the BPR to the FSPDN and electrically connecting the BPR to the transistor device to provide power to the transistor device.

18. The method of claim 17 , wherein connection between the BPR and the FSPDN is formed after forming the array of cells.

19. The method of claim 17 , further comprising forming a power tap cell in the array of cells, the power tap cell electrically connecting the BPR to the FSPDN.

20. The method of claim 17 , further comprising forming a backside power distribution network (BSPDN) on the backside of the device plane, the BSPDN disposed below and connected to the BPR.

Assignees

• Tokyo Electron Ltd

Inventors

• Liebmann Lars
• Smith Jeffrey
• Chanemougame Daniel
• Gutwin Paul

Classifications

• H10W20/481

  on the rear surfaces of the wafers or substrates · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/0698

  Local interconnections · CPC title