Tapered device for lateral gate all around devices

Patent metadata

Field	Value
Publication number	US-12414367-B2
Application number	US-202217882229-A
Country	US
Kind code	B2
Filing date	Aug 5, 2022
Priority date	Sep 15, 2021
Publication date	Sep 9, 2025
Grant date	Sep 9, 2025

Abstract

Aspects of the present disclosure provide a semiconductor structure. For example, the semiconductor structure can include a lower channel structure, an upper channel structure formed vertically over the lower channel, a first transistor device including lower and upper gates formed around a first portion of the lower and upper channel structures, respectively, and a separation layer formed between and separating the lower and upper gates, and a second transistor device including a common gate formed around a second portion of the lower and upper channel structures. The first portion of the lower channel structure is equal to the first portion of the upper channel structure in width, and has a first width less than a second width of the second portion of the lower channel structure.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a lower channel structure;
an upper channel structure formed vertically over the lower channel structure;
a first transistor device including a lower gate formed around a first portion of the lower channel structure, an upper gate formed around a first portion of the upper channel structure, and a separation layer formed between and separating the upper gate and the lower gate; and
a second transistor device including a common gate formed around a second portion of the lower channel structure and a second portion of the upper channel structure,
wherein the first portion of the lower channel structure is equal to the first portion of the upper channel structure in width, the second portion of the lower channel structure is equal to the second portion of the upper channel structure in width, and the first portion of the lower channel structure has a first width less than a second width of the second portion of the lower channel structure.

2. The semiconductor structure of claim 1 , wherein the upper gate is formed all around a cross-section of the upper channel structure, the lower gate is formed all around a cross-section of the lower channel structure, and the common gate is formed all around cross-sections of the upper channel structure and the lower channel structure.

3. The semiconductor structure of claim 1 , wherein the upper channel structure and the lower channel structure have a channel width transition between the first transistor device and the second transistor device.

4. The semiconductor structure of claim 3 , wherein the channel width transition is positioned at a contacted poly pitch (CPP).

5. The semiconductor structure of claim 3 , wherein the channel width transition is step-shaped.

6. The semiconductor structure of claim 5 , wherein the channel width transition is symmetrical with respect to a central line of the upper channel structure and the lower channel structure.

7. The semiconductor structure of claim 1 , further comprising a power rail positioned below the first transistor device and the second transistor device, the power rail having a width corresponding to the widths of the upper channel structure and the lower channel structure.

8. The semiconductor structure of claim 1 , further comprising:
a lower gate contact connected to the lower gate,
wherein a difference between the first width and the second width is sufficient for the lower gate contact to extend from the lower gate to a wiring plane above the first transistor device.

9. The semiconductor structure of claim 1 , further comprising:
a third transistor device that is adjacent to at least one of the first transistor device and the second transistor device,
wherein the lower channel structure and the upper channel structure at the third transistor device have a third width different from at least one of the first width and the second width.

10. A method of manufacturing a semiconductor structure, the method comprising:
forming a mandrel over a semiconductor material layer stack;
forming at least a sidewall spacer on a portion of the mandrel;
using the mandrel and the at least a sidewall spacer to define channel structures in the semiconductor material layer stack;
forming from the semiconductor material layer stack a first transistor device that includes a first portion of the channel structures that corresponds to a first portion of the sidewall spacer and the portion of the mandrel; and
forming from the semiconductor material layer stack a second transistor device that includes a second portion of the channel structures that corresponds to a second portion of the sidewall spacer and the portion of the mandrel,
wherein the first transistor device and the second transistor device are connected by a third portion of the channel structures that corresponds to a remaining of the mandrel.

11. The method of claim 10 , wherein forming at least a sidewall spacer includes forming two sidewall spacers.

12. The method of claim 11 , wherein the two sidewall spacers are formed on two sides of the portion of the mandrel.

13. The method of claim 11 , wherein the two sidewall spacers are formed on one side of the portion of the mandrel.

14. The method of claim 10 , wherein forming at least a sidewall spacer on a portion of the mandrel includes:
forming at least a first sidewall spacer on a portion of the mandrel; and
removing a portion of the at least a first sidewall spacer that is formed on a remaining of the mandrel.

15. A method of manufacturing a semiconductor structure, the method comprising:
forming a lower channel structure;
forming an upper channel structure vertically over the lower channel structure;
forming a first transistor device that includes a lower gate formed around a first portion of the lower channel structure, an upper gate formed around a first portion of the upper channel structure, and a separation layer formed between and separating the upper gate and the lower gate; and
forming a second transistor device that includes a common gate formed around a second portion of the lower channel structure and a second portion of the upper channel structure,
wherein the first portion of the lower channel structure is equal to the first portion of the upper channel structure in width, the second portion of the lower channel structure is equal to the second portion of the upper channel structure in width, and the first portion of the lower channel structure has a first width less than a second width of the second portion of the lower channel structure.

16. The method of claim 15 , wherein the upper channel structure and the lower channel structure have a channel width transition between the first transistor device and the second transistor device.

17. The method of claim 16 , wherein the channel width transition is positioned at a CPP.

18. The method of claim 16 , wherein the channel width transition is step-shaped.

19. The method of claim 15 , further comprising:
forming a lower gate contact connected to the lower gate,
wherein a difference between the first width and the second width is sufficient for the lower gate contact to extend from the lower gate to a wiring plane above the first transistor device.

20. The method of claim 15 , further comprising:
forming a third transistor device that is adjacent to at least one of the first transistor device and the second transistor device,
wherein the lower channel structure and the upper channel structure at the third transistor device have a third width different from at least one of the first width and the second width.

Assignees

• Tokyo Electron Ltd

Inventors

• Liebmann Lars
• Smith Jeffrey
• Chanemougame Daniel
• Gutwin Paul

Classifications

• H10D89/10

  Integrated device layouts · CPC title

• H10D88/01

  Manufacture or treatment · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title

• H10D30/014

  of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title