Self-aligned method for vertical recess for 3D device integration

Patent metadata

Field	Value
Publication number	US-12336274-B2
Application number	US-202217878457-A
Country	US
Kind code	B2
Filing date	Aug 1, 2022
Priority date	Aug 2, 2021
Publication date	Jun 17, 2025
Grant date	Jun 17, 2025

Abstract

Aspects of the present disclosure provide a self-aligned microfabrication method, which can include providing a substrate having vertically arranged first and second channel structures, forming first and second sacrificial contacts to cover ends of the first and second channel structures, respectively, covering the first and second sacrificial contacts with a fill material, recessing the fill material such that the second sacrificial contact is at least partially uncovered while the first sacrificial contact remains covered, replacing the second sacrificial contact with a cover spacer, removing a remaining portion of the first fill material, uncovering the end of the first channel structure, forming a first source/drain (S/D) contact to cover the end of the first channel structure, covering the first S/D contact with a second fill material, uncovering the end of the second channel structure, and forming a second S/D contact at the end of the second channel structure.

First claim

What is claimed is:

1. A method, comprising:
providing a substrate having a first channel structure formed thereon and a second channel structure formed over the first channel structure;
forming a first sacrificial contact and a second sacrificial contact to cover ends of the first channel structure and the second channel structure, respectively;
covering the first sacrificial contact and the second sacrificial contact with a first fill material;
recessing a portion of the first fill material such that the second sacrificial contact is at least partially uncovered while the first sacrificial contact remains covered;
replacing the second sacrificial contact with a cover spacer so that the end of the second channel structure is covered by the cover spacer;
removing a remaining portion of the first fill material;
removing the first sacrificial contact to uncover the end of the first channel structure;
forming a first source/drain (S/D) contact to cover the end of the first channel structure;
covering the first S/D contact with a second fill material;
removing the cover spacer to uncover the end of the second channel structure; and
forming a second S/D contact at the end of the second channel structure.

2. The method of claim 1 , wherein at least one of the first channel structure and the second channel structure includes one or more nanosheets arranged in a vertical stack and separated from one another vertically, and a corresponding one of the first sacrificial contact and the second sacrificial contact that covers the at least one of the first channel structure and the second channel structure covers all of the nanosheets.

3. The method of claim 1 , wherein the first sacrificial contact and the second sacrificial contact are separated from each other.

4. The method of claim 1 , wherein at least one of the first fill material and the second fill material includes pre-metallization dielectric (PMD).

5. The method of claim 1 , wherein at least one of the first sacrificial contact and the second sacrificial contact is un-doped.

6. The method of claim 1 , further comprising:
transferring an interconnect trench into the second fill material with stop once the first S/D contact is uncovered; and
forming within the interconnect trench first interconnect over the first S/D contact.

7. The method of claim 6 , further comprising:
forming a first silicide over the first S/D contact,
wherein the first interconnect is formed over the first silicide.

8. The method of claim 7 , further comprising:
forming a first contact etch stop layer (CESL) over the first S/D contact,
wherein the second fill material further covers the first CESL, and transferring an interconnect trench into the second fill material with stop once the first S/D contact is uncovered includes:
transferring an interconnect trench into the second fill material with stop once a portion of the first CESL is uncovered; and
removing the portion of the first CESL to uncover the first S/D contact.

9. The method of claim 8 , wherein the first CESL and the second fill material are etch-selective.

10. The method of claim 6 , further comprising forming a first interconnect cap overtop the first interconnect.

11. The method of claim 1 , wherein the first fill material and the second sacrificial contact are etch-selective.

12. The method of claim 11 , wherein the first fill material includes dielectric, and the second sacrificial contact includes SiGe.

13. The method of claim 1 , wherein the first sacrificial contact and the first channel structure are etch-selective.

14. The method of claim 13 , wherein the first sacrificial contact includes SiGe, and the first channel structure includes Si.

15. The method of claim 14 , wherein the SiGe of the first sacrificial contact has a Ge content that is set such that maximum selectivity is achieved so that there is no damage or unintended etching of the first channel structure when the first sacrificial contact is removed.

16. The method of claim 1 , further comprising:
laterally recessing the uncovered end of the first channel structure to form a contact extension region,
wherein the first S/D contact is formed in the contact extension region.

17. The method of claim 1 , wherein the first fill material and the second fill material are etch-selective with respect to the cover spacer.

18. A method, comprising:
providing a substrate having a first channel structure formed thereon and a second channel structure formed over the first channel structure;
forming a first sacrificial contact and a second sacrificial contact to cover ends of the first channel structure and the second channel structure, respectively;
covering the first sacrificial contact and the second sacrificial contact with a first fill material;
recessing a portion of the first fill material such that the second sacrificial contact is at least partially uncovered while the first sacrificial contact remains covered;
removing the second sacrificial contact to uncover the end of the second channel structure;
laterally recessing the uncovered end of the second channel structure;
covering the recessed end of the second channel structure with a blocking material;
removing a remaining portion of the first fill material;
removing the first sacrificial contact to uncover the end of the first channel structure;
forming a first S/D contact to cover the end of the first channel structure;
covering the first S/D contact with a second fill material;
removing the blocking material to uncover the recessed end of the second channel structure; and
forming a second S/D contact at the uncovered recessed end of the second channel structure.

19. The method of claim 18 , wherein the first fill material and the second sacrificial contact are etch-selective.

20. The method of claim 18 , wherein the first sacrificial contact and the first channel structure are etch-selective.

Assignees

• Tokyo Electron Ltd

Inventors

• Smith Jeffrey
• Chanemougame Daniel
• Liebmann Lars
• Gutwin Paul
• Kal Subhadeep
• Tapily Kandabara
• Devilliers Anton

Classifications

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W20/427

  Power or ground buses · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/057

  by selectively depositing, e.g. by using selective CVD or plating · CPC title