Method of 3D logic fabrication to sequentially decrease processing temperature and maintain material thermal thresholds

Patent metadata

Field	Value
Publication number	US-11764113-B2
Application number	US-202117392997-A
Country	US
Kind code	B2
Filing date	Aug 3, 2021
Priority date	Oct 20, 2020
Publication date	Sep 19, 2023
Grant date	Sep 19, 2023

Abstract

Techniques herein include methods for fabricating CFET devices. The methods enable high-temperature processes to be performed for FINFET and gate all around (GAA) technologies without degradation of temperature sensitive materials within the device and transistors. In particular, high temperature anneals and depositions can be performed prior to deposition of temperature-sensitive materials, such as work function metals and silicides. The methods enable at least two transistor devices to be fabricated in a stepwise manner while preventing thermal violations of any materials in either transistor.

First claim

What is claimed is:

1. A method of forming a semiconductor device, comprising:
forming a first layer stack on a first wafer;
forming a second layer stack on a second wafer, the second layer stack and the second wafer being separated from the first layer stack and the first wafer;
attaching the first layer stack to the second layer stack via a bonding layer disposed between the first layer stack and the second layer stack;
uncovering the first layer stack without uncovering the second layer stack, the first layer stack being uncovered along an uncovered side of the first layer stack opposite a bonded side of the first layer stack, the bonded side of the first layer stack being proximal to the bonding layer;
forming, at least partially, a first transistor device from the first layer stack;
attaching a first carrier wafer to the uncovered side of the first layer stack;
uncovering the second layer stack, the second layer stack being uncovered along an uncovered side of the second layer stack opposite a bonded side of the second layer stack, the bonded side of the second layer stack being proximal to the bonding layer;
forming, at least partially, a second transistor device from the second layer stack; and
performing a first thermal process on the first transistor device and the second transistor device.

2. The method of claim 1 , further comprising performing additional formation steps on the first transistor device and the second transistor device.

3. The method of claim 2 , further comprising performing a second thermal process on the first transistor device and the second transistor device.

4. The method of claim 3 , wherein the first thermal process is performed at a processing temperature greater than a processing temperature of the second thermal process.

5. The method of claim 2 , further comprising repeating the steps of
attaching a carrier wafer to a target transistor device;
uncovering an untargeted transistor device opposite the target transistor device; and
performing additional formation steps on the target transistor device.

6. The method of claim 5 , further comprising
upon the target transistor device and the untargeted transistor device reaching a same formation step, performing additional thermal processes on the target transistor device and the untargeted transistor device.

7. The method of claim 1 , wherein forming the first transistor device includes forming a PMOS device, and forming the second transistor device includes forming a NMOS device.

8. The method of claim 7 , further comprising connecting the PMOS device and the NMOS device to form a complementary field effect transistor.

9. The method of claim 1 , wherein uncovering the first layer stack further comprises removing material from a second side of the first wafer opposite the first side of the first wafer to uncover the first layer stack.

10. The method of claim 1 , wherein uncovering the second layer stack further comprises removing material from a second side of the second wafer opposite the first side of the second wafer to uncover the second layer stack.

11. The method of claim 1 , wherein attaching the first carrier wafer to the uncovered side of the first layer stack further comprises
filling the uncovered first layer stack with a dielectric fill;
forming a bonding dielectric on the dielectric fill; and
attaching the first carrier wafer to the bonding dielectric.

12. The method of claim 1 , wherein the bonding layer comprises a bonding dielectric material.

13. The method of claim 1 , wherein the first layer stack includes an etch-stop layer disposed between the first layer stack and the first wafer, and the second layer stack includes the etch-stop layer disposed between the second layer stack and the second wafer.

14. The method of claim 13 , wherein uncovering the first layer stack further comprises etching the first wafer until reaching the etch-stop layer, and selectively etching the etch-stop layer.

15. The method of claim 1 , wherein a material of the first wafer and the second wafer is bulk silicon, and uncovering the first layer stack and the second layer stack further comprises removing the bulk silicon material from each wafer to access the respective layer stack.

16. A method of forming a complementary field effect transistor (CFET) device, comprising:
forming a first layer stack on a first wafer;
forming a second layer stack on a second wafer, the second layer stack and the second wafer being separated from the first layer stack and the first wafer;
attaching the first layer stack to the second layer stack via a bonding layer disposed between the first layer stack and the second layer stack;
stepwise accessing each layer stack from each respective side without uncovering the other layer stack at the same time to partially form transistor devices; and
performing a first thermal process on the partially formed transistor devices.

17. The method of claim 16 , wherein stepwise accessing each layer stack further comprises removing wafer material from a given respective side of the combined layer stack while an opposite side of the combined layer stack is protected.

18. The method of claim 17 , further comprising
continuing formation of the transistor devices via alternating access to each layer stack and bonding a carrier wafer to respective sides of the combined layer stack; and
performing a second thermal process on the transistor devices.

19. The method of claim 18 , wherein the first thermal process is performed at a processing temperature greater than a processing temperature of the second thermal process.

20. The method of claim 16 , wherein stepwise accessing each layer from each respective side to partially form transistor devices further comprises forming a PMOS device and forming a NMOS device.

Assignees

• Tokyo Electron Ltd

Inventors

• Smith Jeffrey
• Chanemougame Daniel
• Liebmann Lars
• Gutwin Paul
• Clark Robert
• Devilliers Anton

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P50/00

  Etching of wafers, substrates or parts of devices · CPC title

• H10W72/07331

  Connecting techniques · CPC title

• H10D30/0198

  forming source or drain electrodes wherein semiconductor bodies are replaced by dielectric layers and the source or drain electrodes extend through the dielectric layers · CPC title

• H10D84/0167

  Manufacturing their channels · CPC title