Inverted cross-couple for top-tier FET for multi-tier gate-on-gate 3DI

Patent metadata

Field	Value
Publication number	US-12557377-B2
Application number	US-202217737640-A
Country	US
Kind code	B2
Filing date	May 5, 2022
Priority date	May 13, 2021
Publication date	Feb 17, 2026
Grant date	Feb 17, 2026

Abstract

Aspects of the present disclosure provide a multi-tier semiconductor structure. For example, the semiconductor structure can include a lower semiconductor device tier including lower semiconductor devices, an upper semiconductor device tier disposed over the lower semiconductor device tier and including upper semiconductor devices, a separation layer disposed between and separating the lower and upper semiconductor device tiers, a wiring tier disposed below the lower semiconductor device tier, a lower gate contact extending from a lower gate region of the lower semiconductor device tier downward to the wiring tier, an upper gate contact extending from an upper gate region of the upper semiconductor device tier downward through the separation layer to the wiring tier, and an isolator covering a lateral surface of the upper gate contact and electrically isolating the upper and lower gate contacts. The lower gate contact and the upper gate contact can be independent from each other.

First claim

What is claimed is:

1 . A multi-tier semiconductor structure, comprising:
a lower semiconductor device tier that includes lower semiconductor devices; an upper semiconductor device tier disposed over the lower semiconductor device tier, the upper semiconductor device tier including upper semiconductor devices; a separation layer disposed between and separating the lower semiconductor device tier and the upper semiconductor device tier; a wiring tier disposed below the lower semiconductor device tier; a lower gate contact extending from a lower gate region of the lower semiconductor device tier downward to the wiring tier; an upper gate contact extending from an upper gate region of the upper semiconductor device tier downward through the separation layer to the wiring tier; and an insulator layer disposed between the lower semiconductor device tier and the wiring tier, the lower gate contact and the upper gate contact extending downward to the wiring tier through the insulator layer; an isolator formed to cover a lateral surface of the upper gate contact, the isolator electrically isolating the upper gate contact from the lower gate region, wherein the lower gate contact and the upper gate contact are independent from each other, and the isolator includes a different material from the insulator layer.

2 . The multi-tier semiconductor structure of claim 1 , wherein the wiring tier includes:
a lower wiring track, to which the lower gate contact extends downward; and an upper wiring track, to which the upper gate contact extends downward, wherein the lower wiring track and the upper wiring track are independent from each other.

3 . The multi-tier semiconductor structure of claim 1 , wherein the lower semiconductor devices are vertically stacked on one another, and the upper semiconductor devices are vertically stacked on one another.

4 . The multi-tier semiconductor structure of claim 3 , wherein the lower semiconductor devices include lower GAA semiconductor devices with lower nanosheet channels, and the upper semiconductor devices include upper GAA semiconductor devices with upper nanosheet channels.

5 . The multi-tier semiconductor structure of claim 4 , wherein the lower GAA semiconductor devices include p-type FETs or n-type FETs, and the upper GAA semiconductor devices include p-type FETs or n-type FETs.

6 . The multi-tier semiconductor structure of claim 1 , wherein the isolator includes a dielectric layer.

7 . The multi-tier semiconductor structure of claim 1 , wherein the isolator includes a dielectric block.

8 . The multi-tier semiconductor structure of claim 1 , wherein the insulator layer includes a silicon on insulator (SoI) layer.

9 . The multi-tier semiconductor structure of claim 1 , wherein the insulator includes aluminum oxide (AlO).

Assignees

• Tokyo Electron Ltd

Inventors

• Chanemougame Daniel
• Liebmann Lars
• Smith Jeffrey
• Gutwin Paul

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10D84/0186

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title

• H10D84/0167

  Manufacturing their channels · CPC title

• H10D84/038 Primary

  using silicon technology, e.g. SiGe · CPC title

• H10D62/118

  Nanostructure semiconductor bodies · CPC title