Three-dimensional semiconductor device

Patent metadata

Field	Value
Publication number	US-11764266-B2
Application number	US-202218074684-A
Country	US
Kind code	B2
Filing date	Dec 5, 2022
Priority date	Dec 4, 2020
Publication date	Sep 19, 2023
Grant date	Sep 19, 2023

Abstract

A semiconductor device includes a first field-effect transistor positioned over a substrate, a second field-effect transistor stacked over the first field-effect transistor, a third field-effect transistor stacked over the second field-effect transistor, and a fourth field-effect transistor stacked over the third field-effect transistor. A bottom gate structure is disposed around a first channel structure of the first field-effect transistor and positioned over the substrate. An intermediate gate structure is disposed over the bottom gate structure and around a second channel structure of the second field-effect transistor and a third channel structure of the third field-effect transistor. A top gate structure is disposed over the intermediate gate structure and around a fourth channel structure of the fourth field-effect transistor. An inter-level contact is formed to bypass the intermediate gate structure from a first side of the intermediate gate structure, and arranged between the bottom gate structure and the top gate structure.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor device, the method comprising:
forming a first channel structure over a substrate, a second channel structure over the first channel structure, a third channel structure over the second channel structure, and a fourth channel structure over the third channel structure;
forming a bottom gate structure around the first channel structure;
forming an intermediate gate structure around the second channel structure and the third channel structure;
performing a first etching process to remove a portion of the intermediate gate structure from a first side of the intermediate gate structure so that a portion of the bottom gate structure is uncovered;
forming an inter-level contact that extends from the uncovered portion of the bottom gate structure and bypass the intermediate gate structure from the first side of the intermediate gate structure; and
forming a top gate structure that is disposed over the intermediate gate structure such that the inter-level contact is positioned between the bottom gate structure and the top gate structure.

2. The method of claim 1 , wherein
the first channel structure is formed in a horizontal direction parallel to a top surface of the substrate,
the second channel structure is formed over the first channel structure in the horizontal direction,
the third channel structure is formed over the second channel structure in the horizontal direction, and
the fourth channel structure is formed over the third channel structure in the horizontal direction.

3. The method of claim 2 , wherein each of the first channel structure, the second channel structure, the third channel structure, and the fourth channel structure comprises one or more respective nanosheets that are disposed in the horizontal direction parallel to the top surface of the substrate, stacked over one another, and spaced apart from one another.

4. The method of claim 3 , wherein
the one or more nanosheets of the first channel structure and the one or more nanosheets of the second channel structure include different types of channel materials, and
the one or more nanosheets of the third channel structure and the one or more nanosheets of the fourth channel structure include different types of channel materials.

5. The method of claim 1 , further comprising:
forming a first dielectric cap layer between the bottom gate structure and the intermediate gate structure; and
forming a second dielectric cap layer between the intermediate gate structure and the top gate structure.

6. The method of claim 1 , wherein the inter-level contact is formed to bypass the intermediate gate structure from the first side of the intermediate gate structure.

7. The method of claim 1 , wherein
the first side of the intermediate gate structure extends less than a first side of the top gate structure and a first side of the bottom gate structure from a central axis of the first channel structure, the second channel structure, the third channel structure, and the fourth channel structure, and
a first side of the second channel structure and a first side of the third channel structure extend less than a first side of the first channel structure and a first side of the fourth channel structure from the central axis.

8. The method of claim 1 , wherein the top gate structure and the bottom gate structure are connected to each other through the inter-level contact.

9. The method of claim 1 , further comprising:
performing a second etching process to remove a portion of the top gate structure from a second side of the top gate structure so that a portion of the intermediate gate structure is uncovered from a second side of the intermediate gate structure; and
forming an interconnect contact that extends from the uncovered portion of the intermediate gate structure and bypasses the top gate structure from the second side of the top gate structure.

10. The method of claim 9 , further comprising:
forming a first conductive plane that extends along first sides of the bottom gate structure, the intermediate gate structure, and the top gate structure, and spans a height from the substrate to the fourth channel structure; and
forming a second conductive plane that extends along second sides of the bottom gate structure, the intermediate gate structure, and the top gate structure, and spans the height from the substrate to the fourth channel structure.

11. The method of claim 10 , wherein
the first conductive plane is coupled to one of the bottom gate structure, the intermediate gate structure, and the top gate structure, and
the second conductive plane is coupled to one of the bottom gate structure, the intermediate gate structure, and the top gate structure.

12. The method of claim 10 , further comprising:
forming a fin structure extending from the substrate;
forming a first power rail at a first side of the fin structure and extending into the substrate; and
forming a second power rail at a second side of the fin structure and extending into the substrate.

13. The method of claim 12 , wherein
the first conductive plane is formed to extend from the first power rail, and
the second conductive plane is formed to extend from the second power rail.

14. The method of claim 12 , further comprising:
forming a capping layer for each of the first and second power rails to cover the respective power rail; and
forming a shallow trench isolation (STI) oxide over the substrate and between the fin structure and the first and second power rails.

15. The method of claim 14 , further comprising:
forming a dielectric layer over the STI oxide; and
forming a low-dielectric spacer along sidewalls of the dielectric layer.

16. The method of claim 1 , further comprising:
forming a dielectric liner positioned along the first side of the intermediate gate structure, the dielectric liner being positioned between the intermediate gate structure and the inter-level contact and around the inter-level contact.

17. The method of claim 1 , wherein
the bottom gate structure includes a bottom dielectric stack around the first channel structure, a bottom work function stack around the bottom dielectric stack, and a bottom gate electrode around the bottom workfunction stack,
the intermediate gate structure includes a first intermediate dielectric stack around the second channel structure and a second intermediate dielectric stack around the third channel structure, a first intermediate workfunction stack around the first intermediate dielectric stack, a second intermediate workfunction stack around the second intermediate dielectric stack, and an intermediate gate electrode around the first intermediate work function stack and the second intermediate workfunction stack, and
the top gate structure includes a top dielectric stack around the fourth channel structure, a top workfunction stack around the top dielectric stack, and a top gate electrode around the top workfunction stack.

18. The method of claim 1 , wherein
the bottom gate structure, the first channel structure, a first portion of the intermediate gate structure, and the second channel structure forma first pair of field-effect transistors, and
the top gate structure, the third channel structure, a second portion of the intermediate gate structure, and the fourth channel structure forma second pair of field-effect transistors.

19. A method for manufacturing a semiconductor device, the method comprising:
forming a first channel structure over a subst

Assignees

• Tokyo Electron Ltd

Inventors

• Liebmann Lars
• Smith Jeffrey
• Chanemougame Daniel
• Gutwin Paul

Classifications

• H10D84/8311

  the IGFETs characterised by having different channel structures · CPC title

• H10D30/6757 Primary

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/031

  of thin-film transistors [TFT] · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title