Multi-tier backside power delivery network for dense gate-on-gate 3D logic

Patent metadata

Field	Value
Publication number	US-11830852-B2
Application number	US-202117541581-A
Country	US
Kind code	B2
Filing date	Dec 3, 2021
Priority date	Dec 4, 2020
Publication date	Nov 28, 2023
Grant date	Nov 28, 2023

Abstract

Aspects of the present disclosure provide a multi-tier semiconductor structure. For example, the multi-tier semiconductor structure can include a first power delivery network (PDN) structure, and a first semiconductor device tier disposed over and electrically connected to the first PDN structure. The multi-tier semiconductor structure can further include a signal wiring tier disposed over and electrically connected to the first semiconductor device tier, a second semiconductor device tier disposed over and electrically connected to the signal wiring tier, and a second PDN structure disposed over and electrically connected to the second semiconductor device tier. The multi-tier semiconductor structure can further include a through-silicon via (TSV) structure electrically connected to the signal wiring tier, wherein the TSV structure penetrates the second PDN structure.

First claim

What is claimed is:

1. A multi-tier semiconductor structure, comprising:
a first power delivery network (PDN) structure;
a first semiconductor device tier disposed over and electrically connected to the first PDN structure;
a signal wiring tier disposed over and electrically connected to the first semiconductor device tier;
a second semiconductor device tier disposed over and electrically connected to the signal wiring tier;
a second PDN structure disposed over and electrically connected to the second semiconductor device tier; and
a through-silicon via (TSV) structure electrically connected to the signal wiring tier, the TSV structure penetrating the second PDN structure.

2. The multi-tier semiconductor structure of claim 1 , wherein the TSV structure further penetrates the first PDN structure.

3. The multi-tier semiconductor structure of claim 1 , wherein the signal wiring tier includes multiple wiring levels.

4. The multi-tier semiconductor structure of claim 1 , wherein the TSV structure includes a plurality of TSVs vertically stacked over one another.

5. The multi-tier semiconductor structure of claim 1 , wherein the TSV structure is disposed within a boundary region of the multi-tier semiconductor structure.

6. The multi-tier semiconductor structure of claim 1 , further comprising:
a first substrate disposed between the first semiconductor device tier and the first PDN structure; and
a first power rail buried in the first substrate, the first power rail electrically connecting the first PDN structure to the first semiconductor device tier.

7. The multi-tier semiconductor structure of claim 1 , wherein the first semiconductor device tier includes multiple first semiconductor devices that are vertically stacked over one another.

8. The multi-tier semiconductor structure of claim 1 , further comprising:
another first semiconductor device tier disposed over and electrically connected to the second PDN structure;
another signal wiring tier disposed over and electrically connected to the another first semiconductor device tier;
another second semiconductor device tier disposed over and electrically connected to the another signal wiring tier;
another second PDN structure disposed over and electrically connected to the another second semiconductor device tier; and
another TSV structure electrically connected to the another signal wiring tier, the another TSV structure penetrating at least one of the another first PDN structure and the another second PDN structure.

9. The multi-tier semiconductor structure of claim 1 , further comprising a third PDN structure disposed over the second PDN structure and electrically connected to the TSV structure.

10. A method for fabricating a multi-tier semiconductor structure, the method comprising:
providing a first PDN structure;
disposing a first semiconductor device tier over the first PDN structure and electrically connecting the first semiconductor device tier to the first PDN structure;
disposing a signal wiring tier over the first semiconductor device tier and electrically connecting the signal wiring tier to the first semiconductor device tier;
disposing a second semiconductor device tier over the signal wiring tier and electrically connecting the second semiconductor device tier to the signal wiring tier;
disposing a second PDN structure over the second semiconductor device tier and electrically connecting the second PDN structure to the second semiconductor device tier; and
forming a TSV structure that electrically connects the signal wiring tier and penetrates the second PDN structure.

11. The method of claim 10 , wherein the TSV structure further penetrates the first PDN structure.

12. The method of claim 10 , wherein the signal wiring tier includes multiple wiring levels.

13. The method of claim 12 , wherein:
electrically connecting the signal wiring tier to the first semiconductor device tier includes electrically connecting at least one of the wiring levels of the signal wiring tier to the first semiconductor device tier; and
electrically connecting the second semiconductor device tier to the signal wiring tier includes electrically connecting the second semiconductor device tier to a remainder of the wiring levels of the signal wiring tier and bonding the remainder of the wiring levels to the at least one of the wiring levels.

14. The method of claim 10 , wherein the multi-tier semiconductor structure is fabricated by sequential 3D integration.

15. The method of claim 10 , wherein the TSV structure includes a plurality of TSVs vertically stacked over one another.

16. The method of claim 10 , wherein the TSV structure is disposed within a boundary region of the multi-tier semiconductor structure.

17. The method of claim 10 , further comprising:
disposing a first substrate between the first semiconductor device tier and the first PDN structure; and
burying a first power rail in the first substrate, the first power rail electrically connecting the first PDN structure to the first semiconductor device tier.

18. The method of claim 10 , wherein the first semiconductor device tier includes multiple first semiconductor devices that are vertically stacked over one another.

19. The method of claim 18 , wherein the first semiconductor devices include lateral GAA semiconductor devices that are vertically stacked over one another.

20. The method of claim 10 , further comprising disposing a third PDN structure over the second PDN structure and electrically connecting the third PDN structure to the TSV structure.

Assignees

• Tokyo Electron Ltd

Inventors

• Liebmann Lars
• Smith Jeffrey
• Chanemougame Daniel
• Gutwin Paul
• Cline Brian
• Xu Xiaoqing
• Pietromonaco David

Classifications

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title

• H10W20/481

  on the rear surfaces of the wafers or substrates · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title