Inter-level handshake for dense 3D logic integration

Patent metadata

Field	Value
Publication number	US-12002862-B2
Application number	US-202117328289-A
Country	US
Kind code	B2
Filing date	May 24, 2021
Priority date	Dec 4, 2020
Publication date	Jun 4, 2024
Grant date	Jun 4, 2024

Abstract

A semiconductor device includes a first device plane over a substrate. The first device plane includes a first transistor device having a first source/drain (S/D) region formed in an S/D channel. A second device plane is formed over the first device plane. The second device plane includes a second transistor device having a second gate formed in a gate channel which is adjacent to the S/D channel. A first inter-level connection is formed from the first S/D region of the first transistor device to the second gate of the second transistor device. The first inter-level connection includes a lateral offset from the S/D channel to the gate channel.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first device plane over a substrate, the first device plane including a first transistor device having a first source/drain (S/D) region formed in an S/D channel;
a second device plane over the first device plane, the second device plane including a second transistor device having a second gate formed in a gate channel which is adjacent to the S/D channel; and
a first inter-level connection from the first S/D region of the first transistor device to the second gate of the second transistor device, wherein the first inter-level connection includes a lateral offset from the S/D channel to the gate channel, wherein
the first inter-level connection comprises the S/D channel, a horizontal portion that contacts the S/D channel, and a vertical portion that connects the horizontal portion to the second gate, and
the vertical portion extends from the first device plane to the second device plane and corresponds to a vertical distance from the first S/D region to the second gate relative to a surface of the substrate.

2. The semiconductor device of claim 1 , wherein the horizontal portion corresponds to the lateral offset.

3. The semiconductor device of claim 1 , wherein the first inter-level connection has an L shape in a horizontal cross section parallel to a surface of the substrate.

4. The semiconductor device of claim 1 , wherein the first inter-level connection comprises a conductive metal wiring structure.

5. The semiconductor device of claim 1 , wherein the first transistor device is configured to provide an input signal to the second transistor device.

6. The semiconductor device of claim 1 , further comprising a second inter-level connection that connects a first gate of the first transistor device to a second S/D region in the second device plane.

7. The semiconductor device of claim 2 , wherein the second S/D region is part of the second transistor device in the second device plane.

8. The semiconductor device of claim 6 , wherein the second S/D region is part of a third transistor device in the second device plane.

9. The semiconductor device of claim 1 , wherein the first transistor device and the second transistor device are both complementary field-effect transistors (CFETs).

10. The semiconductor device of claim 1 , wherein:
the first transistor device is an n-type field-effect transistor (FET),
the second transistor device is a p-type FET, and
the first device plane further includes another n-type FET so as to form a CFET with the second transistor device.

11. The semiconductor device of claim 1 , wherein the vertical portion is in direct contact with the horizontal portion.

12. The semiconductor device of claim 1 , wherein the vertical portion is configured to electrically connect the horizontal portion to the second gate.

13. A semiconductor device, comprising:
a pair of CFETs formed over a substrate, the pair of CFETs including an upper CFET positioned over a lower CFET, each CFET including a p-type FET and an n-type FET positioned over each other resulting in a vertical stack of at least four FETs relative to a surface of the substrate; and
an inter-level connection from a pair of complementary gates formed in a gate channel of one CFET to an S/D region formed in an S/D channel of the other CFET, wherein the gate channel of one CFET has a lateral offset from the S/D channel of the other CFET in a horizontal direction along the surface of the substrate and a vertical distance from the S/D channel of the other CFET in a vertical direction relative to the surface of the substrate.

14. The semiconductor device of claim 13 , wherein the inter-level connection comprises:
the S/D channel;
a horizontal portion that is connected to the S/D channel and corresponds to the lateral offset, and
a vertical portion that connects the horizontal portion to the gate channel and corresponds to the vertical distance.

15. The semiconductor device of claim 13 , wherein a gate occupies a respective channel being recessed.

16. The semiconductor device of claim 13 , wherein the inter-level connection is formed from an upper pair of complementary gates of the upper CFET to a lower S/D region of the lower CFET, the semiconductor device further comprising a self-aligned contact that connects the upper pair of complementary gates to one or more structures positioned below the upper pair of complementary gates.

Assignees

• Tokyo Electron Ltd

Inventors

• Liebmann Lars
• Smith Jeffrey
• Chanemougame Daniel
• Gutwin Paul

Classifications

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6729 Primary

  characterised by the electrodes · CPC title

• H10D64/259

  Source or drain electrodes being self-aligned with the gate electrode and having bottom surfaces higher than the interface between the channel and the gate dielectric · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title

• H10D89/10

  Integrated device layouts · CPC title