Interdigitated device stack

Patent metadata

Field	Value
Publication number	US-12224281-B2
Application number	US-202117541609-A
Country	US
Kind code	B2
Filing date	Dec 3, 2021
Priority date	Dec 4, 2020
Publication date	Feb 11, 2025
Grant date	Feb 11, 2025

Abstract

A semiconductor device includes a first pair of transistors over a substrate. The first pair of transistors includes a first transistor having a first gate structure over the substrate and a second transistor having a second gate structure stacked over the first transistor. A second pair of transistors is stacked over the first pair of transistors, resulting in a vertical stack perpendicular to a working surface of the substrate. The second pair of transistors includes a third transistor having a third gate structure stacked over the second transistor and a fourth transistor having a fourth gate structure stacked over the third transistor. The third gate structure extends from a central region of the vertical stack to a first side of the vertical stack. The second gate structure and the fourth gate structure extend from the central region to a second side of the vertical stack opposite the first side.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first pair of transistors positioned over a substrate, the first pair of transistors including a first transistor that has a first gate structure and is positioned over the substrate and a second transistor that has a second gate structure and is stacked over the first transistor; and
a second pair of transistors stacked over the first pair of transistors, resulting in a vertical stack perpendicular to a working surface of the substrate, the second pair of transistors including a third transistor that has a third gate structure and is stacked over the second transistor and a fourth transistor that has a fourth gate structure and is stacked over the third transistor, wherein
the third gate structure extends from a central region of the vertical stack to a first side of the vertical stack,
the second gate structure and the fourth gate structure both extend from the central region of the vertical stack to a second side of the vertical stack opposite the first side of the vertical stack, and
the first gate structure, the second gate structure, the third gate structure and the fourth gate structure are spaced apart from one another.

2. The semiconductor device of claim 1 , further comprising:
a first inter-level contact positioned on the first side of the vertical stack and configured to electrically connect the first gate structure to the third gate structure; and
a second inter-level contact positioned on the second side of the vertical stack and configured to electrically connect the second gate structure to the fourth gate structure.

3. The semiconductor device of claim 2 , wherein:
the first inter-level contact is positioned between the first gate structure and the third gate structure, and
the first inter-level contact bypasses the second gate structure from the first side of the vertical stack.

4. The semiconductor device of claim 2 , wherein:
the second inter-level contact is positioned between the second gate structure and the fourth gate structure, and
the second inter-level contact bypasses the third gate structure from the second side of the vertical stack.

5. The semiconductor device of claim 1 , further comprising:
a first channel structure surrounded by the first gate structure;
a second channel structure surrounded by the second gate structure;
a third channel structure surrounded by the third gate structure; and
a fourth channel structure surrounded by the fourth gate structure.

6. The semiconductor device of claim 5 , wherein:
the first channel structure, the second channel structure, the third channel structure and the fourth channel structure extend in a horizontal direction parallel to the working surface of the substrate.

7. The semiconductor device of claim 6 , wherein:
the first channel structure, the second channel structure, the third channel structure and the fourth channel structure each include one or more respective nanosheets that extend in the horizontal direction and are spaced apart from one another.

8. The semiconductor device of claim 5 , wherein:
the first channel structure, the second channel structure, the third channel structure and the fourth channel structure are positioned in the central region of the vertical stack.

9. The semiconductor device of claim 1 , further comprising:
a first contact structure positioned on the first side of the vertical stack and configured to electrically connect the third gate structure to a first wiring structure.

10. The semiconductor device of claim 9 , further comprising:
a second contact structure positioned over the fourth gate structure and configured to electrically connect the fourth gate structure to a second wiring structure.

11. The semiconductor device of claim 10 , further comprising:
power rails positioned along the first side and the second side of the vertical stack and configured to be electrically connected to the first wiring structure and the second wiring structure.

12. The semiconductor device of claim 9 , wherein:
the first contact structure is positioned over the third gate structure and bypasses the fourth gate structure from the first side of the vertical stack.

13. The semiconductor device of claim 1 , wherein:
the first gate structure extends from the central region of the vertical stack to the first side of the vertical stack, or the first gate structure extends from the central region of the vertical stack to the first side and the second side of the vertical stack.

14. The semiconductor device of claim 1 , wherein:
the first pair of transistors includes a first complementary field-effect transistor (CFET), and
the second pair of transistors includes a second CFET.

15. The semiconductor device of claim 14 , wherein:
the first transistor is a p-type field-effect transistor (FET),
the second transistor is an n-type FET,
the third transistor is an n-type FET, and
the fourth transistor is a p-type FET.

16. A semiconductor device, comprising:
pairs of transistors stacked over a substrate, resulting in a vertical stack perpendicular to a working surface of the substrate, each pair of transistors including a respective top transistor that has a respective top gate and is stacked over a respective bottom transistor having a respective bottom gate, wherein
a plurality of bottom gate structures extends from a central region of the vertical stack to a first side of the vertical stack,
a plurality of top gate structures extends from the central region of the vertical stack to a second side of the vertical stack opposite the first side of the vertical stack,
a first contact structure positioned on the first side of the vertical stack and positioned over a respective bottom gate structure of a topmost pair of transistors and bypasses a respective top gate structure of the topmost pair of transistors from the first side of the vertical stack; and
a second contact structure positioned over the respective top gate structure of the topmost pair of transistors.

17. The semiconductor device of claim 16 , further comprising:
first inter-level contacts positioned on the first side of the vertical stack and each configured to electrically connect two respective bottom gate structures; and
second inter-level contacts positioned on the second side of the vertical stack and each configured to electrically connect two respective top gate structures.

18. The semiconductor device of claim 17 , wherein:
at least one first inter-level contact bypasses a respective top gate structure from the first side of the vertical stack, and
at least one second inter-level contact bypasses a respective bottom gate structure from the second side of the vertical stack.

19. A semiconductor device, comprising:
a first pair of transistors positioned over a substrate, the first pair of transistors including a first transistor that has a first gate structure and is positioned over the substrate and a second transistor that has a second gate structure and is stacked over the first transistor;
a second pair of transistors stacked over the first pair of transistors, resulting in a vertical stack perpendicular to a working surface of the substrate, the second pair of transistors including a third transistor that has a third gate structure and is stacked over the second transistor and a fourth transistor that has a fourth gate structure and is stacked over the third transistor;
a first inter-level contact positioned on the first side of the vertical stack and configur

Assignees

• Tokyo Electron Ltd

Inventors

• Liebmann Lars
• Smith Jeffrey
• Chanemougame Daniel
• Gutwin Paul
• Cline Brian
• Xu Xiaoqing
• Pietromonaco David

Classifications

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title

• H10D84/0172

  Manufacturing their gate conductors · CPC title

• H10D84/853 Primary

  comprising FinFETs · CPC title