Inter-tier power delivery network (PDN) for dense gate-on-gate 3D logic integration

Patent metadata

Field	Value
Publication number	US-12176293-B2
Application number	US-202117541561-A
Country	US
Kind code	B2
Filing date	Dec 3, 2021
Priority date	Dec 4, 2020
Publication date	Dec 24, 2024
Grant date	Dec 24, 2024

Abstract

Aspects of the present disclosure provide a multi-tier semiconductor structure. For example, the multi-tier semiconductor structure can include a lower semiconductor device tier, and a lower signal wiring structure electrically connected to the lower semiconductor device tier. The multi-tier semiconductor structure can further include a primary power delivery network (PDN) structure disposed over the lower semiconductor device tier and the lower signal wiring structure and electrically connected to the lower semiconductor device tier. The multi-tier semiconductor structure can further include an upper semiconductor device tier disposed over and electrically connected the first PDN structure, and an upper signal wiring structure disposed over the primary PDN structure and electrically connected to the upper semiconductor device tier.

First claim

What is claimed is:

1. A multi-tier semiconductor structure, comprising:
a lower semiconductor device tier;
a lower signal wiring structure electrically connected to the lower semiconductor device tier;
a primary power delivery network (PDN) structure disposed over the lower semiconductor device tier and the lower signal wiring structure and electrically connected to the lower semiconductor device tier;
an upper semiconductor device tier disposed over and electrically connected to the primary PDN structure;
an upper signal wiring structure disposed over the primary PDN structure and electrically connected to the upper semiconductor device tier;
a secondary PDN structure disposed between the primary PDN structure and the lower semiconductor device tier and the lower signal wiring structure and electrically connecting the primary PDN structure to the lower semiconductor device tier, the secondary PDN structure being narrower than the primary PDN structure; and
a through-silicon via (TSV) structure that penetrates the primary PDN structure and the secondary PDN structure and directly electrically connects the lower semiconductor device tier to the upper semiconductor device tier.

2. The multi-tier semiconductor structure of claim 1 , wherein the TSV structure includes a plurality of TSVs vertically stacked over one another.

3. The multi-tier semiconductor structure of claim 1 , further comprising:
another lower semiconductor device tier disposed on and electrically connected to the upper signal wiring structure;
another primary PDN structure disposed over the another lower semiconductor device tier and electrically connected to the another lower semiconductor device tier;
another upper semiconductor device tier disposed over and electrically connected to the another primary PDN structure; and
another upper signal wiring structure disposed over the another primary PDN structure and electrically connected to the anther upper semiconductor device tier.

4. The multi-tier semiconductor structure of claim 1 , further comprising:
an upper substrate disposed between the upper semiconductor device tier and the primary PDN structure; and
an upper power rail buried in the upper substrate, the upper power rail electrically connecting the primary PDN structure to the upper semiconductor device tier.

5. The multi-tier semiconductor structure of claim 1 , wherein the upper signal wiring structure is disposed over the upper semiconductor device tier.

6. The multi-tier semiconductor structure of claim 5 , wherein the lower semiconductor device tier is disposed over the lower signal wiring structure.

7. The multi-tier semiconductor structure of claim 6 , wherein the lower semiconductor device tier and the upper semiconductor device tier are symmetrical with respect to the primary PDN structure.

8. The multi-tier semiconductor structure of claim 1 , further comprising a power distribution structure electrically connected to the primary PDN structure, the power distribution structure disposed beyond the upper signal wiring structure and the lower signal wiring structure.

9. The multi-tier semiconductor structure of claim 1 , wherein the upper semiconductor device tier includes multiple upper semiconductor devices that are vertically stacked over one another.

10. The multi-tier semiconductor structure of claim 9 , wherein the upper semiconductor devices include gate-all-around semiconductor devices that are vertically stacked over one another.

11. The multi-tier semiconductor structure of claim 1 , wherein the upper signal wiring structure includes multiple wiring levels.

12. The multi-tier semiconductor structure of claim 1 , wherein the primary PDN structure is sized sufficiently to shield the lower semiconductor device tier when executing annealing when forming the upper semiconductor device tier.

13. A multi-tier semiconductor structure, comprising:
a lower semiconductor device tier;
a lower signal wiring structure electrically connected to the lower semiconductor device tier;
a primary power delivery network (PDN) structure disposed over the lower semiconductor device tier and the lower signal wiring structure and electrically connected to the lower semiconductor device tier;
an upper semiconductor device tier disposed over and electrically connected to the primary PDN structure;
an upper signal wiring structure disposed over the primary PDN structure and electrically connected to the upper semiconductor device tier; and
a power distribution structure electrically connected to the primary PDN structure, the power distribution structure disposed beyond the upper signal wiring structure and the lower signal wiring structure,
wherein the power distribution structure is disposed within a boundary region of the multi-tier semiconductor structure where no semiconductor device tier is disposed, and the primary PDN structure is sized sufficiently to shield the lower semiconductor device tier when executing annealing when forming the upper semiconductor device tier and extends to the boundary region.

14. A method for fabricating a multi-tier semiconductor structure, the method comprising:
providing a lower semiconductor device tier;
electrically connecting a lower signal wiring structure to the lower semiconductor device tier;
disposing a secondary power delivery network (PDN) structure over the lower semiconductor device tier and the lower signal wiring structure;
electrically connecting the secondary PDN structure to the lower semiconductor device tier;
disposing a primary PDN structure over the secondary PDN structure, the primary PDN structure being wider than the secondary PDN structure;
electrically connecting the primary PDN structure to the secondary PDN structure;
disposing an upper semiconductor device tier and an upper signal wiring structure over the primary PDN structure;
electrically connecting the upper semiconductor device tier to the upper signal wiring structure;
electrically connecting the primary PDN structure to the upper semiconductor device tier; and
forming a through-silicon via (TSV) structure that penetrates the primary PDN structure and the secondary PDN structure and directly electrically connects the lower semiconductor device tier to the upper semiconductor device tier.

15. The method of claim 14 , wherein the multi-tier semiconductor structure is fabricated by sequential 3D integration.

16. The method of claim 15 , wherein the primary PDN structure is sized sufficiently to shield the lower semiconductor device tier when executing annealing when forming the upper semiconductor device tier.

Assignees

• Tokyo Electron Ltd

Inventors

• Liebmann Lars
• Smith Jeffrey
• Chanemougame Daniel
• Gutwin Paul
• Cline Brian
• Xu Xiaoqing
• Pietromonaco David

Classifications

• H10W80/00

  Direct bonding of chips, wafers or substrates · CPC title

• H10W20/0253

  comprising forming the through-semiconductor vias after stacking of the chips, wafers or substrates · CPC title

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title