Three-dimensional memory and its fabrication method
US-12557621-B2 · Feb 17, 2026 · US
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Wang Xiangning patents
Wang Xiangning is listed as an inventor on 31 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Wang Xiangning |
| Total patents | 31 |
| First publication | May 6, 2021 |
| Latest publication | Feb 17, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Gateline mask design for removing sacrificial gateline polysilicon within stair step area
US-2026047373-A1 · Feb 12, 2026 · US
Method of forming top select gate trenches
US-12532513-B2 · Jan 20, 2026 · US
Method and structure for forming stairs in three-dimensional memory devices
US-12495555-B2 · Dec 9, 2025 · US
Gateline mask design for removing sacrificial gateline polysilicon within stair step area
US-12469714-B2 · Nov 11, 2025 · US
Three-dimensional memory devices and methods for forming the same
US-12310025-B2 · May 20, 2025 · US
Merging schemes in semiconductive devices
US-2025159881-A1 · May 15, 2025 · US
Methods for forming stairs in three-dimensional memory devices
US-2025038046-A1 · Jan 30, 2025 · US
Semiconductor device fabrication
US-12193229-B2 · Jan 7, 2025 · US
Methods for forming stairs in three-dimensional memory devices
US-12148655-B2 · Nov 19, 2024 · US
Recent patents
Latest publications not already listed above.
Method of forming top select gate trenches
US-2024304693-A1 · Sep 12, 2024 · US
Vertical memory devices
US-12048153-B2 · Jul 23, 2024 · US
Method of forming top select gate trenches
US-12021126-B2 · Jun 25, 2024 · US
Three-dimensional memory devices and methods for forming the same
US-2024206176-A1 · Jun 20, 2024 · US
Gateline mask design for removing sacrificial gateline polysilicon within stair step area
US-2024178001-A1 · May 30, 2024 · US
Three-dimensional memory devices and system having the same
US-2024170389-A1 · May 23, 2024 · US
Three-dimensional memory devices and methods for forming the same
US-11950419-B2 · Apr 2, 2024 · US
Method and structure for forming stairs in three-dimensional memory devices
US-11950418-B2 · Apr 2, 2024 · US
Three-dimensional memory devices having isolation structure for source select gate line and methods for forming the same
US-2023301106-A1 · Sep 21, 2023 · US
Three-dimensional memory devices having isolation structure for source select gate line and methods for forming the same
US-11711921-B2 · Jul 25, 2023 · US
Three-dimensional memory and its fabrication method
US-2023148055-A1 · May 11, 2023 · US
Method and structure for forming stairs in three-dimensional memory devices
US-2023095343-A1 · Mar 30, 2023 · US
Method and structure for forming stairs in three-dimensional memory devices
US-11552097-B2 · Jan 10, 2023 · US
Three-dimensional memory devices and methods for forming the same
US-2022293627-A1 · Sep 15, 2022 · US
Vertical memory devices
US-2022231043-A1 · Jul 21, 2022 · US
Methods for forming stairs in three-dimensional memory devices
US-2022223469-A1 · Jul 14, 2022 · US
Semiconductor device fabrication
US-2022181349-A1 · Jun 9, 2022 · US
Method of forming top select gate trenches
US-2022085181-A1 · Mar 17, 2022 · US
Three-dimensional memory devices having isolation structure for source select gate line and methods for forming the same
US-2022077181-A1 · Mar 10, 2022 · US
Method and structure for forming stairs in three-dimensional memory devices
US-2021249438-A1 · Aug 12, 2021 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Yangtze Memory Tech Co Ltd | 31 |
Top CPC classifications
Most common classification codes across this inventor's patents.