Three-dimensional memory devices and system having the same

Patent metadata

Field	Value
Publication number	US-2024170389-A1
Application number	US-202217991050-A
Country	US
Kind code	A1
Filing date	Nov 21, 2022
Priority date	Nov 21, 2022
Publication date	May 23, 2024
Grant date	—

Abstract

In certain aspects, a three-dimensional (3D) memory device includes a stack structure including alternating conductive layers and dielectric layers and having at least two core regions and a staircase region between the two core regions, and bridge structures connecting the two core regions and extending through the staircase region in a first direction. A first bridge structure of the bridge structures includes at least two current paths between the two core regions.

First claim

What is claimed is:

1 . A three-dimensional (3D) memory device, comprising:
a stack structure comprising alternating conductive layers and dielectric layers and having at least two core regions and a staircase region between the two core regions; and bridge structures connecting the two core regions and extending through the staircase region in a first direction, wherein a first bridge structure of the bridge structures comprises at least two current paths between the two core regions.

2 . The 3D memory device of claim 1 , further comprising:
an isolation structure extending through the staircase region in the first direction; a first slit structure discontinuously extending through the staircase region in the first direction; and a second slit structure discontinuously extending through the staircase region in the first direction, wherein a first current path of the at least two current paths is between the isolation structure and the first slit structure, and a second current path of the at least two current paths is between the first slit structure and the second slit structure.

3 . The 3D memory device of claim 2 , wherein the isolation structure separates two bridge structures in two respective memory blocks.

4 . The 3D memory device of claim 2 , wherein the first current path and the second current path are interconnected through discontinuous portions of the first slit structure.

5 . The 3D memory device of claim 2 , further comprising:
first dummy channel structures extending into the stack structure and being arranged side-by-side in the first direction and in contact with the first slit structure at a close side toward the isolation structure; second dummy channel structures extending into the stack structure and being arranged side-by-side in the first direction and in contact with the first slit structure at a remote side toward the isolation structure; and third dummy channel structures extending into the stack structure and being arranged side-by-side in the first direction and in contact with the second slit structure at a close side toward the isolation structure, wherein the first current path of the at least two current paths is between the isolation structure and the first dummy channel structures, and the second current path of the at least two current paths is between the second dummy channel structures and the third dummy channel structures.

6 . The 3D memory device of claim 5 , wherein a width of the first bridge structure in a remote side toward a substrate is ranged from the isolation structure to that of the third dummy channel structures, and the width of the first bridge structure is no less than 1.25 μm.

7 . The 3D memory device of claim 1 , further comprising: channel structures each extending in the stack structure in the core regions.

8 . The 3D memory device of claim 1 , wherein the first bridge structure connects two of the conductive layers in two respective core regions.

9 . The 3D memory device of claim 1 , wherein a material of the bridge structures comprises tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon (polysilicon), doped silicon, silicides, or any combination thereof.

10 . A three-dimensional (3D) memory device, comprising:
a stack structure comprising alternating conductive layers and dielectric layers and having at least two core regions and a staircase region between the two core regions; bridge structures connecting the two core regions and extending through the staircase region in a first direction; an isolation structure extending through the staircase region in the first direction; a first slit structure discontinuously extending through the staircase region in the first direction; a second slit structure discontinuously extending through the staircase region in the first direction; and at least three dummy channel structures extending into the stack structure and being arranged side-by-side in the first direction and in contact with the first slit structure or the second slit structure.

11 . The 3D memory device of claim 10 , wherein the at least three dummy channel structures comprise:
first dummy channel structures extending into the stack structure and being arranged side-by-side in the first direction and in contact with the first slit structure at a close side toward the isolation structure; second dummy channel structures extending into the stack structure and being arranged side-by-side in the first direction and in contact with the first slit structure at a remote side toward the isolation structure; and third dummy channel structures extending into the stack structure and being arranged side-by-side in the first direction and in contact with the second slit structure at a close side toward the isolation structure.

12 . The 3D memory device of claim 11 , wherein the isolation structure separates two bridge structures in two respective memory blocks.

13 . The 3D memory device of claim 11 , wherein a width of one of the bridge structures in a remote side toward a substrate is ranged from the isolation structure to that of the third dummy channel structures, and the width of the one of the bridge structures is no less than 1.25 μm.

14 . The 3D memory device of claim 11 , further comprising channel structures each extending in the stack structure in the core regions.

15 . The 3D memory device of claim 11 , wherein one of the bridge structures connects two of the conductive layers in two respective core regions.

16 . The 3D memory device of claim 11 , wherein a material of the bridge structures comprises tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon (polysilicon), doped silicon, silicides, or any combination thereof.

17 . A system, comprising:
a three-dimensional (3D) memory device configured to store data, the 3D memory device comprising:
a stack structure comprising alternating conductive layers and dielectric layers and having at least two core regions and a staircase region between the two core regions; and
bridge structures connecting the two core regions and extending through the staircase region in a first direction, wherein a first bridge structure of the bridge structures comprises at least two current paths between the two core regions; and
a memory controller coupled to the 3D memory device and configured to control the 3D memory device.

18 . The system of claim 17 , wherein the 3D memory device further comprises:
an isolation structure extending through the staircase region in the first direction; a first slit structure discontinuously extending through the staircase region in the first direction; and a second slit structure discontinuously extending through the staircase region in the first direction, wherein a first current path of the at least two current paths is between the isolation structure and the first slit structure, and a second current path of the at least two current paths is between the first slit structure and the second slit structure.

19 . The system of claim 18 , wherein the first current path and the second current path are interconnected through discontinuous portions of the first slit structure.

20 . The system of claim 18 , wherein the 3D memory device further comprises:
first dummy channel structures extending into the stack structure and being arranged side-by-side in the first direction and in contact with the first slit structure at a close side toward the isolation structure; second dummy cha

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Wu Jiajia
• Yuan Bin
• Xu Zongke
• Guo Zhen
• Li Beibei
• Wang Xiangning
• Yang Zhu
• Zhang Qiangwei
• Huo Zongliang

Classifications

• H10W20/432 Primary

  comprising crossing interconnections · CPC title

• H01L23/5221 Primary

  Electricity · mapped topic

• H01L27/11556

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title