Semiconductor device fabrication

Patent metadata

Field	Value
Publication number	US-12193229-B2
Application number	US-202117213471-A
Country	US
Kind code	B2
Filing date	Mar 26, 2021
Priority date	Dec 4, 2020
Publication date	Jan 7, 2025
Grant date	Jan 7, 2025

Abstract

Aspects of the disclosure provide methods for fabricating semiconductor devices. In some examples, a method for fabricating a semiconductor device includes forming a stack of layers having a first region and a second region. The stack of layers includes at least a first layer. The method then forms a hard mask layer on the stack of layers in the first region. Then, the method includes patterning the stack of layers in the second region of the semiconductor device. The patterning of the stack of layers in the second region removes a portion of the stack of layers in the second region, and exposes a side of the stack of layers. The method further includes covering at least the side of the stack of layers with a second layer that has a lower remove rate than the first layer, and then the method includes removing the hard mask layer.

First claim

What is claimed is:

1. A method for fabricating a semiconductor device, comprising:
forming a stack of layers having a first region and a second region, the stack of layers including at least a first layer;
forming a hard mask layer on the stack of layers in the first region of the semiconductor device;
patterning the stack of layers in the second region of the semiconductor device, the patterning of the stack of layers in the second region removing a portion of the stack of layers in the second region, and exposing a side of the stack of layers;
depositing in the first region and the second region a second layer that has a lower remove rate than the first layer, the second layer overfilling the portion of the stack of layers in the second region and covering the side of the stack of layers and the hard mask layer in the first region;
removing a portion of the second layer that covers a portion of the hard mask layer to expose the portion of the hard mask layer, with a remaining portion of the hard mask layer still covered by the second layer;
planarizing a remaining portion of the second layer that is in the second region and still covers the remaining portion of the hard mask layer until the second layer is leveled with the exposed portion of the hard mask layer and the remaining portion of the hard mask layer is exposed; and
removing the hard mask to expose the stack of layers in the first region of the semiconductor device and planarizing the second layer such that the second layer is leveled with the exposed stack of layers in the semiconductor device,
wherein no intermediate step is performed between removing the portion of the second layer and planarizing the remaining portion of the second layer.

2. The method of claim 1 , wherein the first layer includes a sacrificial layer and the second layer includes an insulating layer.

3. The method of claim 1 , wherein the hard mask layer is removed by at least a wet etchant hat comprises phosphoric acid.

4. The method of claim 1 , wherein the stack of layers comprises a stack of alternatingly stacked sacrificial layers and insulating layers, and the sacrificial layers include the first layer.

5. The method of claim 4 , wherein patterning the stack of layers in the second region of the semiconductor device further comprises:
forming, in the second region, stair steps in the stack of alternatingly stacked sacrificial layers and insulating layers, sides of the stair steps exposing the sacrificial layers.

6. The method of claim 5 , wherein covering at least the side of the stack of layers with the second layer that has the lower remove rate than the first layer further comprises:
depositing the second layer in the first region and the second region, the second layer overfilling the second region.

7. The method of claim 6 , wherein depositing the second layer further comprises:
depositing silicon oxide using tetraethoxysilane (TEOS).

8. The method of claim 1 , wherein the remaining portion of the second layer is planarized by a chemical mechanical polishing (CMP) process.

9. The method of claim 8 , wherein the CMP process stops on the hard mask layer.

10. The method of claim 1 , wherein the hard mask layer is formed of a material with a dielectric constant higher than 4.

11. The method of claim 10 , wherein the hard mask layer comprises at least one of Ta 2 O 5 , SrTiO 3 , Al 2 O 3 , TiN, W, or polysilicon.

12. A method for fabricating a semiconductor device, comprising:
forming a stack of layers having a first region and a second region;
forming a hard mask layer on the stack of layers in the first region;
patterning the stack of layers in the second region into stair steps, the patterning of the stack of layers in the second region removing a portion of the stack of layers in the second region and forming a space in the second region;
depositing insulating filler material in the first region and the second region, the insulating filler material filling the space in the second region;
removing a portion of the insulating filler material that covers a portion of the hard mask layer to expose the portion of the hard mask laver, with a remaining portion of the hard mask layer still covered by the insulating filler material;
planarizing a remaining portion of the insulating filler material that is in the second region and still covers the remaining portion of the hard mask layer until the insulating filler material is leveled with the exposed portion of the hard mask layer and the remaining portion of the hard mask is exposed; and
removing the hard mask to expose the stack of layers in the first region of the semiconductor device and planarizing the insulating filler material such that the insulating filler material is leveled with the exposed stack of layers in the semiconductor device,
wherein no intermediate step is performed between removing the portion of the insulating filler material and planarizing the remaining portion of the insulating filler material.

13. The method of claim 12 , wherein removing the hard mask layer further comprises:
removing the hard mask layer using a chemical mechanical polishing (CMP) process.

14. The method of claim 12 , wherein removing the hard mask layer further comprises:
removing the hard mask layer using a wet bench approach with phosphoric acid.

15. The method of claim 12 , wherein removing the hard mask layer further comprises:
removing the hard mask layer using a combination of a chemical mechanical polishing (CMP) process and a wet bench approach with phosphoric acid.

16. The method of claim 12 , wherein the hard mask layer is formed of a material with a dielectric constant higher than 4.

17. The method of claim 16 , wherein the hard mask layer comprises at least one of Ta 2 O 5 , SrTiO 3 , Al 2 O 3 , TiN, W, or polysilicon.

18. The method of claim 17 , wherein patterning the stack of layers in the second region into stair steps further comprises:
forming, in the second region, the stair steps in the stack of alternatingly stacked sacrificial layers and insulating layers, sides of the stair steps exposing the sacrificial layers.

19. The method of claim 12 , wherein the stack of layers comprises a stack of alternatingly stacked sacrificial layers and insulating layers.

20. The method of claim 12 , wherein depositing the insulating filler material further comprises:
depositing silicon oxide using tetraethoxysilane (TEOS).

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Yuan Bin
• Yang Zhu
• Wang Xiangning
• Zuo Chen
• Geng Jingjing
• Guo Zhen
• Xu Zongke
• Zhang Qiangwei

Classifications

• H10P50/73 Primary

  using masks for insulating materials · CPC title

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/50

  characterised by the boundary region between the core and peripheral circuit regions · CPC title

• H10B41/50

  characterised by the boundary region between the core region and the peripheral circuit region · CPC title