Three-dimensional memory device including inclined word line contact strips and methods of forming the same
US-2024414916-A1 · Dec 12, 2024 · US
characterised by the boundary region between the core region and the peripheral circuit region
characterised by the boundary region between the core region and the peripheral circuit region · Cooperative Patent Classification (CPC)
Electric circuits, power, telecommunications, and semiconductors.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | H10B41/50 |
| Official title | characterised by the boundary region between the core region and the peripheral circuit region |
| Display label | characterised by the boundary region between the core region and the peripheral circuit region |
| Total patents | 3,610 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is growing.
| Year | Patents |
|---|---|
| 2015 | 100 |
| 2016 | 142 |
| 2017 | 134 |
| 2018 | 161 |
| 2019 | 211 |
| 2020 | 378 |
| 2021 | 394 |
| 2022 | 460 |
| 2023 | 414 |
| 2024 | 581 |
| 2025 | 502 |
| 2026 | 133 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Semiconductor devices and data storage systems including the same
US-2024297117-A1 · Sep 5, 2024 · US
Method for fabricating three-dimensional semiconductor device using buried stop layer in substrate
US-2024268119-A1 · Aug 8, 2024 · US
Integrated Assemblies Having Conductive Posts Extending Through Stacks of Alternating Materials
US-2024237336-A9 · Jul 11, 2024 · US
Semiconductor integrated circuit device including split selection lines and method of manufacturing the semiconductor integrated circuit device
US-2024196613-A1 · Jun 13, 2024 · US
Semiconductor memory device and manufacturing method of the semiconductor memory device
US-2024172440-A1 · May 23, 2024 · US
Method for fabricating layer structure having target topological profile
US-2024128090-A1 · Apr 18, 2024 · US
Staircase formation in three-dimensional memory device
US-11961760-B2 · Apr 16, 2024 · US
Methods of forming microelectronic devices including stair step structures
US-2024071930-A1 · Feb 29, 2024 · US
Semiconductor device and method for manufacturing the same
US-2015380426-A1 · Dec 31, 2015 · US
Vertical NAND device with shared word line steps
US-9224747-B2 · Dec 29, 2015 · US
Semiconductor device and method of manufacturing the same
US-2015371944-A1 · Dec 24, 2015 · US
Stacked 3D memory with isolation layer between memory blocks and access conductors coupled to decoding elements in memory blocks
US-9202750-B2 · Dec 1, 2015 · US
Flash memory devices and fabrication method thereof
US-2015318294-A1 · Nov 5, 2015 · US
Stair step formation using at least two masks
US-2015318203-A1 · Nov 5, 2015 · US
Method of fabricating semiconductor device and device fabricated thereby
US-9171853-B2 · Oct 27, 2015 · US
Three-dimensional nonvolatile memory device
US-9171860-B2 · Oct 27, 2015 · US
Semiconductor device and method of manufacturing the same
US-9165938-B1 · Oct 20, 2015 · US
Semiconductor device and method of manufacturing the same
US-9165774-B2 · Oct 20, 2015 · US
Memory device comprising a memory cell and a selection transistor
US-9153598-B2 · Oct 6, 2015 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC H10B41/50?
- CPC H10B41/50 is the Cooperative Patent Classification code for “characterised by the boundary region between the core region and the peripheral circuit region.”
- How many patents are filed under CPC H10B41/50 (characterised by the boundary region between the core region and the peripheral circuit region)?
- Our database includes 3,610 publications tagged with this CPC code.
- Is patent activity under CPC H10B41/50 growing?
- Publication counts under this code: 581 in 2024 vs 502 in 2025 (latest complete years).