Three-dimensional memory and its fabrication method

Patent metadata

Field	Value
Publication number	US-12557621-B2
Application number	US-202218089463-A
Country	US
Kind code	B2
Filing date	Dec 27, 2022
Priority date	Nov 9, 2021
Publication date	Feb 17, 2026
Grant date	Feb 17, 2026

Abstract

A method of fabricating a three-dimensional memory includes forming a laminated structure including stacked dummy gate layers and interlayer insulation layers on one side of a substrate. The respective adjacent dummy gate layers and interlayer insulation layers form staircase stairs. At least a part of the interlayer insulation layer of each of the staircase stairs is exposed. The method also includes forming a buffer layer covering the staircase stairs. The method further includes removing a part of the buffer layer covering the sidewalls of the staircase stairs to form spacing grooves. The method further includes forming a dielectric layer that fills the spacing grooves and covers the staircase stairs. The method further includes forming a contact hole penetrating through the dielectric layer and the buffer layer and extending to the dummy gate layer farthest from the substrate.

First claim

What is claimed is:

1 . A three-dimensional memory, comprising:
a laminated structure including stacked gate layers and interlayer insulation layers, wherein a first gate layer of the gate layers and a first interlayer insulation layer of the interlayer insulation layers form a first staircase stair, the first gate layer being adjacent to the first interlayer insulation layer at a first side of the first interlayer insulation layer; a conductor layer on an end of the first interlayer insulation layer and, in a lateral direction, separated from a second gate layer of the gate layers through a portion of a dielectric layer, the second gate layer being adjacent to the first interlayer insulation layer at a second side of the first interlayer insulation layer; and a contact structure vertically penetrating through the dielectric layer, the conductor layer, and the first interlayer insulation layer in this order and extending into the first gate layer, wherein: the conductor layer and the second gate layer are aligned along a same vertical level; and a bottom of the portion of the dielectric layer, between the second gate layer and the conductor layer, is positioned below the vertical level.

2 . The three-dimensional memory according to claim 1 , further comprising:
the dielectric layer covering sidewalls of the conductor layer.

3 . The three-dimensional memory according to claim 2 , wherein the first interlayer insulation layer and the dielectric layer comprise different insulating materials.

4 . The three-dimensional memory according to claim 1 , wherein materials of the first gate layer and the conductor layer both include tungsten.

5 . The three-dimensional memory according to claim 1 , wherein the first gate layer to which the contact structure extends is one of the gate layers that is closest to the conductor layer in a vertical direction perpendicular to the lateral direction.

6 . The three-dimensional memory according to claim 1 , wherein the contact structure penetrates through a portion of the first gate layer.

7 . The three-dimensional memory according to claim 1 , further comprising:
the dielectric layer covering sidewalls and a top surface of the conductor layer.

8 . The three-dimensional memory according to claim 1 , wherein a material of the dielectric layer and a material of the first interlayer insulation layer are identical.

9 . The three-dimensional memory according to claim 1 , wherein the portion of the dielectric layer is configured to cover sidewalls of the first staircase stair.

10 . The three-dimensional memory according to claim 1 , wherein a material of the conductor layer and a material of the first gate layer are identical.

11 . The three-dimensional memory according to claim 1 , wherein the end of the first interlayer insulation layer is sandwiched between the conductor layer and the first gate layer.

12 . The three-dimensional memory of claim 1 , wherein an end of the conductor layer is flush with the end of the first interlayer insulation layer in a vertical direction perpendicular to the lateral direction.

13 . The three-dimensional memory of claim 1 , wherein the dielectric layer is a multi-layer structure.

14 . The three-dimensional memory of claim 1 , further comprising:
the dielectric layer comprising a tetraethyl orthosilicate (TEOS) based silicon oxide layer.

15 . The three-dimensional memory of claim 1 , further comprises:
the dielectric layer comprising a first sub-film layer and a second sub-film layer on the first sub-film layer, a density of the first sub-film layer being higher than a density of the second sub-film layer.

16 . The three-dimensional memory of claim 1 , wherein the contact structure comprises tungsten.

17 . The three-dimensional memory of claim 1 , wherein a portion of the first gate layer is configured to surround a first portion of the contact structure.

18 . The three-dimensional memory of claim 1 , wherein the conductor layer is configured to surround a second portion of the contact structure.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Guo Zhen
• Yuan Bin
• Xu Zongke
• Wu Jiajia
• Li Beibei
• Wang Xiangning
• Yang Zhu
• Zhang Qiangwei

Classifications

• H10W20/4441 Primary

  the principal metal being a refractory metal · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10B43/50

  characterised by the boundary region between the core and peripheral circuit regions · CPC title

• H10B41/50

  characterised by the boundary region between the core region and the peripheral circuit region · CPC title