Merging schemes in semiconductive devices

Patent metadata

Field	Value
Publication number	US-2025159881-A1
Application number	US-202318389652-A
Country	US
Kind code	A1
Filing date	Dec 19, 2023
Priority date	Nov 14, 2023
Publication date	May 15, 2025
Grant date	—

Abstract

The present disclosure relates methods, devices, systems, and techniques for merging schemes in semiconductor devices such as three-dimensional (3D) semiconductor devices. In one aspect, a semiconductor device includes a semiconductor structure that includes a stack of conductive layers and insulating layers alternating with each other along a first direction. The semiconductor structure includes an array region and a connection region adjacent to the array region in a second direction perpendicular to the first direction. The semiconductor device further includes multiple contact structures extending through the connection region along the first direction. Each conductive layer in the stack of conductive layers and insulating layers is coupled to a corresponding contact structure of the multiple contact structures and isolated from one or more other contact structures of the multiple contact structures. Each contact structure of the multiple contact structures includes a body and a head extending beyond the body.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a semiconductor structure comprising a stack of conductive layers and insulating layers alternating with each other along a first direction, wherein the semiconductor structure comprises an array region and a connection region adjacent to the array region in a second direction perpendicular to the first direction; and multiple contact structures extending through the connection region along the first direction, wherein each conductive layer in the stack of conductive layers and insulating layers is coupled to a corresponding contact structure of the multiple contact structures and isolated from one or more other contact structures of the multiple contact structures, and wherein each contact structure of the multiple contact structures comprises a body and a head extending beyond the body, an end of the head is in contact with an end of the body, and the end of the body is wider than the end of the head.

2 . The semiconductor device of claim 1 , wherein the body comprises an outer layer, an inner layer, and an intermediate layer between the outer layer and the inner layer, the head comprises an outer layer, an inner layer, and an intermediate layer between the outer layer and the inner layer, and the outer layer of the body, the intermediate layer of the body, and the inner layer of the body are continuously connected with the outer layer of the head, the intermediate layer of the head, and the inner layer of the head, respectively.

3 . The semiconductor device of claim 2 , wherein the outer layer of the body comprises a high-k dielectric material, the intermediate layer of the body comprises a titanium nitride material, the inner layer of the body comprises a conductive material, the outer layer of the head comprises a high-k dielectric material, the intermediate layer of the head comprises a titanium nitride material, and the inner layer of the head comprises a conductive material.

4 . The semiconductor device of claim 1 , wherein the contact structure extends through a set of conductive layers of the stack of conductive layers and insulating layers, wherein the contact structure is in contact with one conductive layer of the set of conductive layers that is closest to the head of the contact structure among the set of conductive layers, and wherein a contact spacer comprising a dielectric material is located between the contact structure and one or more other conductive layers of the set of conductive layers that are isolated from the contact structure.

5 . The semiconductor device of claim 1 , wherein the semiconductor structure comprises one or more decks that are sequentially stacked together along the first direction, and
wherein the body of the contact structure comprises one or more segments that are sequentially connected together along the first direction, and each of the one or more segments is shaped like a truncated cone and corresponds to a respective deck of the one or more decks of the semiconductor structure.

6 . The semiconductor device of claim 4 , further comprising gate line slits and channel structures both extending through the semiconductor structure along the first direction.

7 . A method, comprising:
providing a semiconductor structure comprising sacrificial layers and insulating layers alternating with each other along a first direction, wherein the semiconductor structure comprises one or more decks sequentially stacked in the first direction, and each deck of the one or more decks comprises a subset of the sacrificial layers and the insulating layers, and wherein the semiconductor structure comprises an array region and a connection region adjacent to the array region in a second direction perpendicular to the first direction; and forming: a) first gate line holes in the array region, b) second gate line holes and contact holes in the connection region, c) first channel holes in the array region, and d) second channel holes in the connection region, wherein the first gate line holes, the second gate line holes, the contact holes, the first channel holes, and the second channel holes extend through the semiconductor structure along the first direction, and wherein the first gate line holes, the second gate line holes, the contact holes, the first channel holes, and the second channel holes in each deck of the one or more decks are formed during a same etching process.

8 . The method of claim 7 , wherein the connection region comprises an isolation structure, and a protective layer is formed between the isolation structure and the sacrificial layers.

9 . The method of claim 8 , further comprising:
filling the first channel holes, the second channel holes, the first gate line holes, the second gate line holes, and the contact holes with a polysilicon material.

10 . The method of claim 9 , further comprising:
forming channel structures in the first channel holes and the second channel holes.

11 . The method of claim 10 , further comprising:
etching and recessing the sacrificial layers exposed by the contact holes using a first etchant having a faster etching rate for the sacrificial layers than the protective layer; forming a contact spacer layer in each of the contact holes, wherein the contact spacer layer is in contact with the recessed sacrificial layers; and etching and recessing the protective layer exposed by each of the contact holes using a second etchant having a faster etching rate for the protective layer than the contact spacer layer in each of the contact holes.

12 . The method of claim 11 , further comprising:
filling the contact holes with a sacrificial material; polishing a top surface of the semiconductor structure; and depositing an isolating layer on the top surface of the semiconductor structure.

13 . The method of claim 12 , further comprising:
forming a gate line opening in the isolating layer for each of the first and second gate line holes to expose the first and second gate line holes; removing the polysilicon material in the first and second gate line holes; and expanding the first and second gate line holes to form multiple gate line trenches extending in the second direction, wherein each of the multiple gate line trenches comprises a series of expanded gate line holes connected with each other along the second direction.

14 . The method of claim 13 , further comprising:
oxidizing a bottom surface of each of the multiple gate line trenches, wherein the bottom surface is in a substrate of the semiconductor structure.

15 . The method of claim 14 , further comprising:
forming a contact opening in the isolating layer for each contact hole of the contact holes, wherein a width of the contact opening is smaller than a width of the contact hole; and removing the sacrificial material in the contact holes.

16 . The method of claim 15 , further comprising:
removing the sacrificial layers in the semiconductor structure.

17 . The method of claim 16 , further comprising:
depositing at least one conductive material into the multiple gate line trenches and the contact holes to form conductive layers between the insulating layers and contact structures extending through the connection region of the semiconductor structure in the first direction, wherein each conductive layer of the conductive layers is connected to a corresponding contact structure of the contact structures and is isolated from one or more other contact structures of the contact structures, wherein each contact structure of the contact structures comp

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Li Beibei
• Yuan Bin
• Xu Zongke
• Wang Xiangning
• Xu Wei

Classifications

• H10B43/40

  characterised by the peripheral circuit region · CPC title

• H10B43/35

  with cell select transistors, e.g. NAND · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B41/41

  of a memory region comprising a cell select transistor, e.g. NAND · CPC title

• H10B41/35

  with a cell select transistor, e.g. NAND · CPC title