Gateline mask design for removing sacrificial gateline polysilicon within stair step area

Patent metadata

Field	Value
Publication number	US-12469714-B2
Application number	US-202218090031-A
Country	US
Kind code	B2
Filing date	Dec 28, 2022
Priority date	Nov 29, 2022
Publication date	Nov 11, 2025
Grant date	Nov 11, 2025

Abstract

A semiconductor device includes a stack of alternating word line layers and insulating layers. The stack includes a core area, a stair step area, and, optionally, a dummy transition area connecting the core area to the stair step area. The semiconductor device also includes a gate line (GL) trench through the stack extending from the core area through the dummy transition area to the stair step area. The GL trench has a first width within the core area and a second width within the stair step area that is different from the first width. The semiconductor device also includes a first channel structure formed through the stack within the core area, and a stair step contact (SCT) formed through at least a portion of the stack within the stair step area. The SCT connects one of the word line layers of the stack within the stair step area.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a stack of alternating word line layers and insulating layers, the stack including a core area and a stair step area connected to the core area; one or more gate line (GL) structures through the word line layers and the insulating layers of the stack, the GL structures extending from the core area to the stair step area, at least one of the GL structures having a first width within the core area and a second width within the stair step area that is different from the first width; one or more first channel structures formed through the stack within the core area; and one or more stair step contacts (SCTs) each formed through at least a portion of the stack within the stair step area, the SCTs each connecting one of the word line layers of the stack within the stair step area.

2 . The semiconductor device of claim 1 , wherein the second width is greater than the first width.

3 . The semiconductor device of claim 2 , wherein the second width is 1 + -3 times greater than the first width.

4 . The semiconductor device of claim 2 , further comprising a dummy transition area connected between the stair step area and the core area, wherein the GL structure within the dummy transition area has a width monotonously decreased from a first end connected to the stair step area to a second end connected to the core area.

5 . The semiconductor device of claim 1 , further comprising:
another stack of alternating dielectric layers and insulating layers within the stair step area, the another stack of alternating dielectric layers and insulating layers being in contact with the stack of alternating word line layers and insulating layers within the stair step area.

6 . The semiconductor device of claim 5 , wherein each layer of the another stack of alternating dielectric layers and insulating layers is in line with a corresponding layer of the stack of alternating word layers and insulating layers.

7 . The semiconductor device of claim 1 , wherein the SCTs each includes a vertical portion through the portion of the stack within the stair step area and a horizontal portion connected to a bottom end of the vertical portion at a center thereof and to one of the word line layers within the stair step area that the portion of the stack reaches.

8 . A method, comprising:
providing a stack of alternating sacrificial layers and insulating layers over a substrate, the stack including a core area and a stair step area connected to the core area; forming one or more gate line (GL) trenches through the sacrificial layers and the insulating layers of the stack extending from the core area to the stair step area; and filling the GL trenches with a first trench filler material such that the first trench filler material in at least one of the GL trenches within one of the core area and the stair step area is hollow.

9 . The method of claim 8 , wherein the GL trench within the other of the core area and the stair step area is fully filled by the first trench filler material.

10 . The method of claim 8 , wherein the GL trench has a first width within the one of the core area and the stair step area and a second width within the other of the core area and the stair step area that is different from the first width.

11 . The method of claim 10 , wherein the second width is less than the first width.

12 . The method of claim 11 , further comprising:
removing the first trench filler material in the GL trench within the one of the core area and the stair step area; and removing and replacing a portion of the sacrificial layers of the stack within the one of the core area and the stair step area with a first conductive layer.

13 . The method of claim 12 , wherein the one of the core area and the stair step area is the stair step area, and the method further comprises:
forming within the stair step area a stair step contact (SCT) through at least a portion of the stack that connects the first conductive layer.

14 . The method of claim 13 , further comprising:
removing the first trench filler material in the GL trench within the core area; and removing and replacing the sacrificial layers of the stack within the core area with a second conductive layer.

15 . The method of claim 14 , further comprising:
filling the GL trench within the core area and the stair step area with a second trench filler material.

16 . The method of claim 15 , wherein filling the GL trench within the core area and the stair step area with the second trench filler material includes:
filling the second trench filler material in the GL trench until a first predetermined number of holes is formed in the second trench filler material in the GL trench within the core area; etching back the second trench filler material in the GL trench until the first predetermined number of holes is opened; filling the second trench filler material in the GL trench until a second predetermined number of holes is formed in the second trench filler material in the GL trench within the stair step area; etching back the second trench filler material in the GL trench within the stair step area until the second predetermined number of holes is opened; and filling the second trench filler material in the GL trench within the stair step area.

17 . The method of claim 13 , wherein the SCT is formed by:
forming within the stair step area an SCT opening through the portion of the stack to uncover lateral sides of the insulating layers and the sacrificial layers of the portion of the stack and one of the sacrificial layers that the portion of the stack reaches; forming a spacer that covers the lateral sides of the insulating layers and the sacrificial layers; removing a portion of the one of the sacrificial layers to form a space; forming a liner to cover the spacer and fill the space; removing the sacrificial layers of the stack within the stair step area; replacing the sacrificial layers of the stack within the core area and a portion of the sacrificial layers within the stair step area with the first conductive layer; and filling a metal material in the space and the SCT opening to connect the first conductive layer.

18 . The method of claim 8 , further comprising:
filling the hollow first trench filler material with a second trench filler material.

19 . The method of claim 18 , wherein the second trench filler material does not interface with the first trench filler material.

20 . A memory system, comprising:
a semiconductor device, including:
a stack of alternating word line layers and insulating layers, the stack including a core area and a stair step area connected to the core area;
one or more gate line (GL) structure through the word line layers and the insulating layers of the stack extending from the core area to the stair step area, at least one of the GL structures having a first width within the core area and a second width within the stair step area that is different from the first width;
one or more first channel structures formed through the stack within the core area; and
one or more stair step contacts (SCTs) each formed through at least a portion of the stack within the stair step area, the SCTs each connecting one of the word line layers of the stack within the stair step area; and
control circuitry coupled to the semiconductor device, the control circuitry configured for controlling operations of the semiconductor device.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Li Beibei
• Xu Wei
• Yuan Bin
• Xu Zongke
• Wang Xiangning
• Huo Zongliang

Classifications

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10P50/73 Primary

  using masks for insulating materials · CPC title

• H10B41/20

  characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels · CPC title

• H10B43/20 Primary

  characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels · CPC title

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title