Three-dimensional memory devices having isolation structure for source select gate line and methods for forming the same

Patent metadata

Field	Value
Publication number	US-11711921-B2
Application number	US-202017084378-A
Country	US
Kind code	B2
Filing date	Oct 29, 2020
Priority date	Sep 4, 2020
Publication date	Jul 25, 2023
Grant date	Jul 25, 2023

Abstract

Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack on the substrate, a plurality of channel structures each extending vertically through the memory stack, an isolation structure, and an alignment mark. The memory stack includes a plurality of interleaved conductive layers and dielectric layers. An outmost one of the conductive layers toward the substrate is a source select gate line (SSG). The isolation structure extends vertically into the substrate and surrounds at least one of the channel structures in a plan view to separate the SSG and the at least one channel structure. The alignment mark extends vertically into the substrate and is coplanar with the isolation structure.

First claim

What is claimed is:

1. A three-dimensional (3D) memory device, comprising:
a substrate;
a memory stack on the substrate comprising a plurality of interleaved conductive layers and dielectric layers, an outermost one of the conductive layers toward the substrate being a source select gate line (SSG);
a plurality of first channel structures each extending vertically through the memory stack in a core array region;
an isolation structure extending vertically into the substrate in an edge region and surrounding at least one second channel structure in a plan view to separate the SSG and the at least one second channel structure, wherein the edge region is laterally between a staircase region and the core array region; and
an alignment mark extending vertically into the substrate in the staircase region and coplanar with the isolation structure.

2. The 3D memory device of claim 1 , wherein the plurality of first channel structures are disposed in the core array region in the plan view, and the at least one second channel structure is disposed in the edge region.

3. The 3D memory device of claim 2 , wherein the memory stack comprises a staircase structure, the edge region is laterally between the staircase structure and the core array region, and the at least one second channel structure is disposed in an outmost column adjacent to the staircase structure in the plan view.

4. The 3D memory device of claim 2 , wherein a lateral dimension of the at least one second channel structure is greater than a lateral dimension of the first channel structures disposed in the core array region.

5. The 3D memory device of claim 1 , wherein a lateral distance between the SSG and the at least one second channel structure is between about 40 nm and about 80 nm.

6. The 3D memory device of claim 1 , wherein each of the at least one second channel structure comprises a semiconductor plug at one end toward the substrate.

7. The 3D memory device of claim 6 , wherein the isolation structure is laterally between the SSG and the semiconductor plug of the at least one second channel structure.

8. The 3D memory device of claim 6 , wherein the semiconductor plug of the at least one second channel structure extends into the substrate further than a semiconductor plug of another one of the first channel structures.

9. The 3D memory device of claim 1 , wherein the isolation structure and the alignment mark each comprise a dielectric.

10. The 3D memory device of claim 1 , wherein the alignment mark extends vertically through the SSG.

11. The 3D memory device of claim 1 , further comprising an SSG cut extending vertically into the substrate and coplanar with the isolation structure and the alignment mark.

12. A three-dimensional (3D) memory device, comprising:
a substrate;
a source select gate line (SSG) extending laterally;
an isolation structure extending vertically through the SSG into the substrate in an edge region;
a first channel structure extending vertically through the SSG into the substrate in a core array region;
a second channel structure extending vertically through the isolation structure into the substrate in the edge region and spaced apart from the SSG by the isolation structure; and
a memory stack comprising a plurality of interleaved conductive layers and dielectric layers, wherein the SSG is an outermost one of the conductive layers toward the substrate, the memory stack comprises a staircase structure, the edge region is laterally between the staircase structure and the core array region, and the second channel structure in the edge region is disposed in an outmost column adjacent to the staircase structure in a plan view.

13. The 3D memory device of claim 12 , wherein the second channel structure extends into the substrate further than the first channel structures.

14. The 3D memory device of claim 12 , further comprising:
an alignment mark extending vertically through the SSG into the substrate and coplanar with the isolation structure; and
an SSG cut extending vertically through the SSG into the substrate and coplanar with the isolation structure and the alignment mark.

15. The 3D memory device of claim 14 , wherein the isolation structure and the alignment mark each comprise a dielectric.

16. The 3D memory device of claim 12 , wherein
each of the first and second channel structures comprises a semiconductor plug at one end thereof;
the semiconductor plug of the first channel structure is in contact with the SSG; and
the semiconductor plug of the second channel structure is in contact with the isolation structure.

17. The 3D memory device of claim 12 , wherein a lateral dimension of the second channel structures is greater than a lateral dimension of the first channel structure.

18. The 3D memory device of claim 12 , wherein a lateral distance between the SSG and the second channel structure is between about 40 nm and about 80 nm.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Guo Zhen
• Geng Jingjing
• Yuan Bin
• Wu Jiajia
• Wang Xiangning
• Yang Zhu
• Zuo Chen

Classifications

• H10W46/301

  for alignment · CPC title

• H10W46/00 Primary

  Marks applied to devices, e.g. for alignment or identification · CPC title

• H10W10/0143 Primary

  comprising concurrently refilling multiple trenches having different shapes or dimensions · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title